公开(公告)号：US20240126354A1

公开(公告)日：2024-04-18

申请号：US18399224

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Kunal Shah ,  Prabhakar Subrahmanyam ,  Venkataramani Gopalakrishnan ,  Chuen Ming Tan ,  Venkataramana Kotakonda ,  Mitsu Shah ,  Kannappan Rajaraman ,  Yi Jen Huang ,  Dmitriy Berchanskiy ,  Swathi Nukala

IPC: G06F1/26 ,  G06F1/3203

CPC classification number: G06F1/266 ,  G06F1/3203

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for power budgeting for computer peripherals with electronic devices. An example apparatus to budget power in an electronic device includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: detect a Type-C event associated with a computer peripheral; write a power level offset based on an assumed power contract for the computer peripheral during debounce time; obtain an actual power contract for the computer peripheral; and adjust the power level offset based on the actual power contract.

公开(公告)号：US11705750B2

公开(公告)日：2023-07-18

申请号：US17125814

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Udaya Natarajan ,  Kannappan Rajaraman ,  Venkat Jayaraman

IPC: H02J7/00 ,  G06F1/3212 ,  G06F1/3287 ,  G06F9/4401

CPC classification number: H02J7/007 ,  G06F1/3212 ,  G06F1/3287 ,  G06F9/4401 ,  H02J7/0042

Abstract: A power sequence in a power-delivery (PD) mechanism (interaction between host system components and a charger) and a firmware sequence during power contract negotiation reduces the host system power consumption at or below the pSnkStdby power limit to improve user experience and battery life. The power sequence uses USB Type-C PD protocol and timing specification to implement a synchronous trigger or interrupt and interface mechanism. The synchronous trigger or interrupt and interface mechanism between a PD controller and an embedded controller firmware controls the power consumption dynamically during the boot flow sequence to be less than or equal to pSnkStdby power limit while implementing a predictable boot sequence and optimizing boot time. The power negotiating sequence is also applicable when a source (e.g., a charger) is connected to a SoC host system which is in active state (e.g., S0) and when there is an indication of low battery capacity.

公开(公告)号：US20220037899A1

公开(公告)日：2022-02-03

申请号：US16943941

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： Udaya Shankar Natarajan ,  Kannappan Rajaraman

IPC: H02J7/00 ,  G06F1/26 ,  G06F13/42

Abstract: A software and hardware architecture framework utilize the specifications of Universal Serial Bus (USB) Type-C and Power Deliver (PD) to provide fine grain throttling of a processor (e.g., system-on-chip (SoC)). Based on an external charger connection or disconnection, a low latency fine grain power budget loss or gain indication to the processor is delivered. The mechanism of various embodiments is also applicable to connection or disconnection of VBUS powered peripheral devices to the system. The net power loss or gain available to the SoC and System is proportionally used to scale the processor throttling.

公开(公告)号：US20210408803A1

公开(公告)日：2021-12-30

申请号：US17125814

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Udaya Natarajan ,  Kannappan Rajaraman ,  Venkat Jayaraman

IPC: H02J7/00 ,  G06F1/3287 ,  G06F9/4401 ,  G06F1/3212

Abstract: A power sequence in a power-delivery (PD) mechanism (interaction between host system components and a charger) and a firmware sequence during power contract negotiation reduces the host system power consumption at or below the pSnkStdby power limit to improve user experience and battery life. The power sequence uses USB Type-C PD protocol and timing specification to implement a synchronous trigger or interrupt and interface mechanism. The synchronous trigger or interrupt and interface mechanism between a PD controller and an embedded controller firmware controls the power consumption dynamically during the boot flow sequence to be less than or equal to pSnkStdby power limit while implementing a predictable boot sequence and optimizing boot time. The power negotiating sequence is also applicable when a source (e.g., a charger) is connected to a SoC host system which is in active state (e.g., S0) and when there is an indication of low battery capacity.

公开(公告)号：US20250103539A1

公开(公告)日：2025-03-27

申请号：US18474001

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Kannappan Rajaraman ,  Udaya Natarajan

IPC: G06F13/42

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus includes a USB-C port; power delivery circuitry to determine, based on a mode-support message accessed via the USB-C port, that an external device supports Compute Express Link (CXL) as a standalone protocol over USB-C; and multiplexer management circuitry to cause the power delivery circuitry to transmit a CXL status message to the external device via the USB-C port.

公开(公告)号：US20230385218A1

公开(公告)日：2023-11-30

申请号：US17826933

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Udaya Natarajan ,  Kannappan Rajaraman ,  Huimin Chen

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/382 ,  G06F13/4282 ,  G06F2213/0042 ,  G06F2213/3812

Abstract: Embodiments herein relate to a universal serial bus (USB) host system that is configured to perform port orientation identification and/or configuration lane identification. Specifically, the USB host system may include a USB Type-C port configured to communicate in accordance with the USB 3.2 protocol. The described identifications may be performed without the use of a power delivery (PD) and/or Type-C port controller (TCPC) module. Other embodiments may be described and claimed.

公开(公告)号：US20230305615A1

公开(公告)日：2023-09-28

申请号：US17705012

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Udaya Natarajan ,  Kannappan Rajaraman

IPC: G06F1/3212 ,  H02J50/80 ,  G06F13/42 ,  H02J7/00

CPC classification number: G06F1/3212 ,  H02J50/80 ,  G06F13/4282 ,  H02J7/0049 ,  H02J7/00034

Abstract: Techniques and mechanisms for opportunistically charging a battery with a programmable power adapter. In an embodiment, a charger circuit is to be coupled between the programmable power adapter and a load circuit which is coupled to the battery. Bypass circuitry is coupled to selectively enable a bypassing of the charger circuit. Based on a state of charge of the battery, a controller circuit identifies a power delivery scheme which includes both an operational mode of the programmable power adapter, and an activation state of the switch circuit. The controller configures the identified power delivery scheme by signaling that the programmable power adapter is to be transitioned to the operational mode. In another embodiment, the operational mode is based on communications which are compatible with a Universal Serial Bus (USB) standard protocol.

公开(公告)号：US12259768B2

公开(公告)日：2025-03-25

申请号：US17448597

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Aruni P. Nelson ,  Udaya Natarajan ,  Kannappan Rajaraman

IPC: G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F13/10

Abstract: In an embodiment, a host system for selecting a power supply includes a processor, a bus interface to connect to a peripheral device, and a power controller. The power controller may be to: determine whether the processor has entered a reduced power mode; determine, via one or more bus messages, whether charging is to be performed for a battery of the peripheral device; and in response to a determination that the processor has entered the reduced power mode and that charging is not to be performed for the battery of the peripheral device, switch from a first power supply to a second power supply as an active power source of the host system. Other embodiments are described and claimed.

公开(公告)号：US12164355B2

公开(公告)日：2024-12-10

申请号：US17203561

申请日：2021-03-16

Applicant: Intel Corporation

Inventor： Udaya Natarajan ,  Kannappan Rajaraman

IPC: G06F1/3215 ,  G06F1/26 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/4401

Abstract: A power saving apparatus and method for a host system to proactively decide to save power and increase battery life when bus powered peripheral devices are connected to the System's USB TYPE-C ports. The Host (or Host System) decides if a Bus Powered Device (BPD), hub or a peripheral device requires application services, or a device-initiated wake based on wake policies of a respective Universal Serial Bus (USB) 3.2, THUNDERBOLT 3 (TBT3), USB4, DISPLAYPORT (DP) Protocol. Thereafter, the Host decides based on S0, Low Power System standby entry—wake time latency requirement along with USB TYPE-C IO Protocol policies, to trigger the system power delivery (PD) Controller to remove power to the BPD. To save power, the Host System Wake logic power partition is also powered off.

公开(公告)号：US20230111694A1

公开(公告)日：2023-04-13

申请号：US17448597

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Aruni P. Nelson ,  Udaya Natarajan ,  Kannappan Rajaraman

IPC: G06F1/26 ,  G06F1/3203 ,  G06F13/10

Abstract: In an embodiment, a host system for selecting a power supply includes a processor, a bus interface to connect to a peripheral device, and a power controller. The power controller may be to: determine whether the processor has entered a reduced power mode; determine, via one or more bus messages, whether charging is to be performed for a battery of the peripheral device; and in response to a determination that the processor has entered the reduced power mode and that charging is not to be performed for the battery of the peripheral device, switch from a first power supply to a second power supply as an active power source of the host system. Other embodiments are described and claimed.