公开(公告)号：US20240192755A1

公开(公告)日：2024-06-13

申请号：US18077131

申请日：2022-12-07

Applicant: Intel Corporation

Inventor： Chuen Ming Tan ,  Venkataramani Gopalakrishnan ,  Aneesh Tuljapurkar ,  Vishwanath Somayaji ,  Tabassum Yasmin

IPC: G06F1/3225 ,  G06F1/3287

CPC classification number: G06F1/3225 ,  G06F1/3287

Abstract: Embodiments herein relate to a circuit which allows the re-use of an existing power supply units having main power rails and an auxiliary power rail, while supporting large memory configurations in a sleep state to avoid data loss. A processor determines whether a power requirement of memory modules in a computing device exceeds an available power of the auxiliary power rail. If this is the case, the processor asserts an override signal which is used by a logic circuit to force the power supply to remain on in the sleep state. A set of switches disconnect the main rails from other components which can be turned off in the sleep state. A select circuit selects one of the main rails to power the memory modules.

公开(公告)号：US20240019918A1

公开(公告)日：2024-01-18

申请号：US18472833

申请日：2023-09-22

Applicant: Intel Corporation

Inventor： Ravi Verma ,  Saunak Bhalsod ,  Venkataramani Gopalakrishnan ,  Archana Rao ,  Raghavendra Rao ,  Tomer Savariego ,  Chuen Ming Tan ,  Manjunatha V

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: A power delivery architecture is described that improves system voltage conversion and operational efficiency. The power delivery architecture performs monitoring of various system conditions such as a current power state, a current power policy setting, workload conditions, component temperatures, a state of charge of a battery, etc. The power delivery architecture may adjust the power profile provided by a power delivery source, which may result in an adjustment to the VBUS voltage and/or current when a USB-based power delivery architecture is implemented. The power delivery architecture may also adjust a mode of operation of an onboard battery charger.

公开(公告)号：US20230350479A1

公开(公告)日：2023-11-02

申请号：US17732096

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Venkataramani Gopalakrishnan ,  Chuen Ming Tan ,  Divagar Mohandass ,  Dmitriy Berchanskiy ,  Nirmala Bailur ,  Timothy Smith ,  Rajaram Regupathy

IPC: G06F1/3215 ,  G06F1/3212 ,  G06F1/3296

CPC classification number: G06F1/3215 ,  G06F1/3212 ,  G06F1/3296

Abstract: Systems, apparatuses and methods may provide for technology that allocates a portion of operational power in a source device to an external sink device in response to a connection of the external sink device to the source device, detects a low power state with respect to the external sink device, and decreases the portion of operational power allocated to the external sink device in response to the low power state.

公开(公告)号：US20240126354A1

公开(公告)日：2024-04-18

申请号：US18399224

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Kunal Shah ,  Prabhakar Subrahmanyam ,  Venkataramani Gopalakrishnan ,  Chuen Ming Tan ,  Venkataramana Kotakonda ,  Mitsu Shah ,  Kannappan Rajaraman ,  Yi Jen Huang ,  Dmitriy Berchanskiy ,  Swathi Nukala

IPC: G06F1/26 ,  G06F1/3203

CPC classification number: G06F1/266 ,  G06F1/3203

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for power budgeting for computer peripherals with electronic devices. An example apparatus to budget power in an electronic device includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: detect a Type-C event associated with a computer peripheral; write a power level offset based on an assumed power contract for the computer peripheral during debounce time; obtain an actual power contract for the computer peripheral; and adjust the power level offset based on the actual power contract.

公开(公告)号：US20240104043A1

公开(公告)日：2024-03-28

申请号：US17950840

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Shailendra Singh Chauhan ,  Nirmala Bailur ,  Reza M. Zamani ,  Jackson Chung Peng Kong ,  Charuhasini Sunder Raman ,  Venkataramani Gopalakrishnan ,  Chuen Ming Tan ,  Sreejith Satheesakurup ,  Karthi Kaliswamy ,  Venkata Mahesh Gunnam ,  Yi Jen Huang ,  Kie Woon Lim ,  Dhinesh Sasidaran ,  Pik Shen Chee ,  Venkataramana Kotakonda ,  Kunal A. Shah ,  Ramesh Vankunavath ,  Siva Prasad Jangili Ganga ,  Ravali Pampala ,  Uma Medepalli ,  Tomer Savariego ,  Naznin Banu Wahab ,  Sindhusha Kodali ,  Manjunatha Venkatarauyappa ,  Surendar Jeevarathinam ,  Madhura Shetty ,  Deepak Sharma ,  Rohit Sharad Mahajan

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4045 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0042

Abstract: Embodiments herein relate to a module which can be inserted into or removed from a computing device by a user. The module includes an input-output port which is configured for a desired specification, such as USB-A, USB-C, Thunderbolt, DisplayPort or HDMI. The port can be provided on an expansion card such as an M.2 card for communicating with a host platform. The host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. In another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.

公开(公告)号：US20230409100A1

公开(公告)日：2023-12-21

申请号：US17841550

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Shailendra Singh Chauhan ,  Arvind Sundaram ,  Manasa Nagamangala Sridhara ,  Anil Kumar Nama ,  Ramesh Vankunavath ,  Manjunath Channipura Hombaiah ,  Siva Prasad Jangili Ganga ,  Kunal Shah ,  Venkata Mahesh Gunnam ,  Chuen Ming Tan ,  Venkataramana Kotakonda

IPC: G06F1/30 ,  G06F1/28

CPC classification number: G06F1/30 ,  G06F1/28

Abstract: Embodiments herein relate to a power monitor that can be used to dynamically change a power level of an electronic device and/or operational settings of a processor of the electronic device. Specifically, the power monitor may be configured to identify “droop” of power, and logic to update the power level and/or operational settings in accordance with identification of the droop. Other embodiments may be described and claimed.

公开(公告)号：US20230093974A1

公开(公告)日：2023-03-30

申请号：US17448798

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Chuen Ming Tan ,  Venkataramani Gopalakrishnan ,  Nirmala Bailur ,  Tai Loong Wong ,  Yi How Ooi ,  Sze Geat Pang ,  Wei Cheang Lau

IPC: G06F1/3234 ,  G06F1/3212 ,  G06F1/26

Abstract: In an embodiment, a computing system for selecting a power mode may include: a system load, a battery, a power converter to receive external power and provide output power, and a processor to: monitor a charge level of the battery while the computing system is in a converter power mode, where the converter power mode comprises to power the system load and charge the battery from the output power of the power converter; and in response to a determination that the charge level of the battery is within a battery condition range, cause the computing system to switch from the converter power mode to a battery power mode, where the battery power mode comprises, during a connection of the power converter to the external power, to disconnect the battery from the power converter and power the system load from output power of the battery.