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公开(公告)号：US20230273811A1
公开(公告)日：2023-08-31
申请号：US17682091
申请日：2022-02-28
Applicant: Intel Corporation
Inventor： Michael Mishaeli , Eyal Oz-Sinay , Gavri Berger , Gal Ofir , Tomer Weiner , Arkady Bramnik
CPC classification number: G06F9/4843 , G06F9/22
Abstract: In one embodiment, an apparatus includes: an instruction fetch circuit to fetch instructions; a decode circuit coupled to the instruction fetch circuit to decode the fetched instructions into micro-operations (pops); a scheduler coupled to the decode circuit to schedule the pops for execution; and an execution circuit coupled to the scheduler, the execution circuit comprising a plurality of execution ports to execute the pops. The scheduler may be configured to: schedule at least some pops of a first type for redundant execution on symmetric execution ports of the plurality of execution ports; and schedule pops of a second type for non-redundant execution on a single execution port of the plurality of execution ports. Other embodiments are described and claimed.
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公开(公告)号：US20160103785A1
公开(公告)日：2016-04-14
申请号：US14881111
申请日：2015-10-12
Applicant: Intel Corporation
Inventor： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
CPC classification number: G06F15/8007 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3887
Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
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公开(公告)号：US10152451B2
公开(公告)日：2018-12-11
申请号：US15490743
申请日：2017-04-18
Applicant: Intel Corporation
Inventor： Zeev Sperber , Robert Valentine , Shlomo Raikin , Stanislav Shwartsman , Gal Ofir , Igor Yanover , Guy Patkin , Ofer Levy
Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
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公开(公告)号：US10146737B2
公开(公告)日：2018-12-04
申请号：US14616323
申请日：2015-02-06
Applicant: Intel Corporation
Inventor： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
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公开(公告)号：US09501132B2
公开(公告)日：2016-11-22
申请号：US14453341
申请日：2014-08-06
Applicant: Intel Corporation
Inventor： Michael Mishaeli , Stanislav Shwartsman , Gal Ofir , Yulia Kurolap
CPC classification number: G06F1/3287 , G06F1/32 , G06F9/30145 , G06F15/7807 , Y02D10/171 , Y02D50/20
Abstract: A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit. The decode unit includes logic to decode a store broadcast instruction of a specified width. The LPG includes logic to selectively provide power to the locally-gated circuitry, activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations, and deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry. The execution unit includes logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.
Abstract translation: 处理器包括具有本地门控电路的核心，解码单元，耦合到本地门控电路的本地电源门（LPG）以及执行单元。 解码单元包括用于解码指定宽度的存储广播指令的逻辑。 LPG包括用于选择性地向本地门控电路提供电力的逻辑，激活本地门控电路的第一部分以执行完全高速缓存行存储器操作的功率，以及去激活局部门控电路的第二部分的功率 本地门控电路。 执行单元包括由用于执行全高速缓存行存储器操作的本地门控电路的第一部分执行存储广播指令，存储广播指令以存储指定宽度的数据以存储处理器的逻辑。
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Patent Agency Ranking
公开(公告)号：US09396056B2
公开(公告)日：2016-07-19
申请号：US14214910
申请日：2014-03-15
Applicant: Intel Corporation
Inventor： Zeev Sperber , Robert Valentine , Offer Levy , Michael Mishaeli , Gal Ofir
CPC classification number: G06F11/079 , G06F11/0721 , G06F11/073
Abstract: In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode stage to decode one or more instruction specifying: a set of memory operations, one or more register, and one or more memory address. One or more execution units, responsive to the one or more decoded instruction, generate said one or more memory address for the set of memory operations. Instruction execution logic records one or more fault suppress bits to indicate whether one or more portion of the set of memory operations are masked. Fault generation logic is suppressed from considering a memory fault corresponding to a faulting one of the set of memory operations when said faulting one of the set of memory operations corresponds to a portion of the set of memory operations that is indicated as masked by said one or more fault suppress bits.
Abstract translation: 在一些公开的实施例中，指令执行逻辑提供条件存储器故障辅助抑制。 处理器的一些实施例包括解码级，以对一个或多个指令进行解码，该指令指定：一组存储器操作，一个或多个寄存器和一个或多个存储器地址。 响应于一个或多个解码指令的一个或多个执行单元为该组存储器操作生成所述一个或多个存储器地址。 指令执行逻辑记录一个或多个故障抑制位以指示该组存储器操作中的一个或多个部分被屏蔽。 当所述一组存储器操作中的所述故障之一对应于由所述一组存储器操作屏蔽的所述一组存储器操作的一部分时，故障产生逻辑被抑制为考虑与所述一组存储器操作中的故障的一个存储器操作相对应的存储器故障， 更多的故障抑制位。
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公开(公告)号：US09753889B2
公开(公告)日：2017-09-05
申请号：US14881111
申请日：2015-10-12
Applicant: Intel Corporation
Inventor： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
CPC classification number: G06F15/8007 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3887
Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
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公开(公告)号：US20170192934A1
公开(公告)日：2017-07-06
申请号：US14616323
申请日：2015-02-06
Applicant: Intel Corporation
Inventor： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
CPC classification number: G06F15/8007 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3887
Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
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公开(公告)号：US20160041945A1
公开(公告)日：2016-02-11
申请号：US14453341
申请日：2014-08-06
Applicant: Intel Corporation
Inventor： Michael Mishaeli , Stanislav Shwartsman , Gal Ofir , Yulia Kurolap
CPC classification number: G06F1/3287 , G06F1/32 , G06F9/30145 , G06F15/7807 , Y02D10/171 , Y02D50/20
Abstract: A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit. The decode unit includes logic to decode a store broadcast instruction of a specified width. The LPG includes logic to selectively provide power to the locally-gated circuitry, activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations, and deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry. The execution unit includes logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.
Abstract translation: 处理器包括具有本地门控电路的核心，解码单元，耦合到本地门控电路的本地电源门（LPG）以及执行单元。 解码单元包括用于解码指定宽度的存储广播指令的逻辑。 LPG包括用于选择性地向本地门控电路提供电力的逻辑，激活本地门控电路的第一部分以执行完全高速缓存行存储器操作的功率，以及去激活局部门控电路的第二部分的功率 本地门控电路。 执行单元包括由用于执行全高速缓存行存储器操作的本地门控电路的第一部分执行存储广播指令，存储广播指令以存储指定宽度的数据以存储处理器的逻辑。
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公开(公告)号：US20150074373A1
公开(公告)日：2015-03-12
申请号：US13977727
申请日：2012-06-02
Applicant: INTEL CORPORATION
Inventor： Zeev Sperber , Robert Valentine , Shlomo Raikin , Stanislav Shwartsman , Gal Ofir , Igor Yanover , Guy Patkin , Levy Ofer
CPC classification number: G06F15/7839 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3808 , G06F9/383
Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
Abstract translation: 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码散射/收集指令并产生微操作。 索引数组保存一组索引和一组对应的掩码元素。 有限状态机有助于散射操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 正在生成的每组地址的缓冲区中分配存储空间。 与生成的地址集相对应的数据元素被复制到缓冲器。 如果对应的掩码元素具有所述第一值并且掩模元素被响应于它们各自的存储的完成而被改变为第二值，则访问该集合的地址以存储数据元素。
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