公开(公告)号：US09458283B2

公开(公告)日：2016-10-04

申请号：US14746750

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： Dingying Xu ,  Nisha Ananthakrishnan ,  Hong Dong ,  Rahul N. Manepalli ,  Nachiket R. Raravikar ,  Gregory S. Constable

IPC: C08G77/04 ,  C08L63/00 ,  B32B27/38 ,  C08G59/02 ,  C08L23/08 ,  H01L21/56 ,  H01L23/29 ,  C08G59/32 ,  C08G59/38 ,  C07F7/08 ,  H01L23/00

CPC classification number: C08G59/02 ,  C07F7/0838 ,  C08G59/3254 ,  C08G59/38 ,  C08L23/0884 ,  H01L21/563 ,  H01L23/293 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3512 ,  Y10T428/31515 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

公开(公告)号：US20160151850A1

公开(公告)日：2016-06-02

申请号：US15017398

申请日：2016-02-05

Applicant: Intel Corporation

Inventor： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

IPC: B23K1/00 ,  B23K1/20 ,  H01L23/367

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K1/203 ,  B23K3/085 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251 ,  Y10T428/12222

Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

Abstract translation: 形成封装结构的方法和相关结构包括在IHS的阻焊剂开口位置上形成低熔点焊料材料，从而在非SRO保护区域内形成密封剂; 将IHS连接到密封剂上，并固化密封剂，其中在IHS和低熔点焊料材料之间形成焊接接头。

公开(公告)号：US09808875B2

公开(公告)日：2017-11-07

申请号：US15017398

申请日：2016-02-05

Applicant: Intel Corporation

Inventor： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

IPC: B23K31/00 ,  B23K31/02 ,  B23K1/00 ,  B23K3/08 ,  B23K1/20 ,  H01L23/367

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K1/203 ,  B23K3/085 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251 ,  Y10T428/12222

Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.