公开(公告)号：US10484361B2

公开(公告)日：2019-11-19

申请号：US15199356

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Timothy J. Callahan ,  Baruch Schnarch ,  Hem Doshi ,  Suketu U. Bhatt

IPC: H04L29/06 ,  G06F13/42 ,  G06F11/30 ,  G06F21/85

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; a transaction originator to originate a transactions and issue the transactions onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transactions at the serial IO interface via the device fabric and return responsive transactions to the device originator based on the transactions received; signature collection logic to collect signal information based on the transactions carried by the device fabric; and a signal accumulator to generate a test signature based on the signal information collected by the signature collection logic. Other related embodiments are disclosed.

公开(公告)号：US11789516B2

公开(公告)日：2023-10-17

申请号：US17440688

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC: G06F1/00 ,  G06F1/324

CPC classification number: G06F1/324

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US10664433B2

公开(公告)日：2020-05-26

申请号：US15199323

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Timothy J. Callahan ,  Hem Doshi ,  Hooi Kar Loo ,  Suketu U. Bhatt

IPC: G06F13/42 ,  H04L29/06 ,  G06F21/82

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a shuttle transaction and to issue the shuttle transaction onto the device fabric directed toward the serial IO interface; in which the shuttle transaction includes a shuttle header and a shuttle payload having embedded therein one or more passenger transactions for issuance onto the device fabric; in which the virtualized device logic is to receive the shuttle transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to strip the shuttle header from the shuttle transaction to expose the one or more passenger transactions; and in which the virtualized device logic is to issue the one or more passenger transactions onto the device fabric. Other related embodiments are disclosed.

公开(公告)号：US20220179473A1

公开(公告)日：2022-06-09

申请号：US17440688

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC: G06F1/324

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US09389906B2

公开(公告)日：2016-07-12

申请号：US14138761

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Hem Doshi ,  Anand Raju

IPC: G06F9/46 ,  G06F13/362 ,  G06F13/16 ,  G06F12/08 ,  H04L12/937

CPC classification number: G06F9/467 ,  G06F12/084 ,  G06F13/1605 ,  G06F13/362 ,  H04L49/254

Abstract: According to one embodiment, an apparatus includes a transaction data storage to store transaction data to be transmitted over an interconnect of a data processing system, a transaction buffer coupled to the transaction data storage to buffer at least a portion of the transaction data, and a transaction logic coupled to the transaction data storage and the transaction buffer to transmit a request (REQ) signal to an arbiter associated with the interconnect in response to first transaction data that becomes available in the transaction data storage, in response to a grant (GNT) signal received from the arbiter, retrieve second transaction data from the transaction buffer and transmit the second transaction data onto the interconnect, and refill the transaction buffer with third transaction data retrieved from the transaction data storage after the second transaction data has been transmitted onto the interconnect.

Abstract translation: 根据一个实施例，一种装置包括交易数据存储器，用于存储要通过数据处理系统的互连发送的交易数据，耦合到交易数据存储器的交易缓冲器以缓冲交易数据的至少一部分，以及 交易逻辑耦合到交易数据存储器和事务缓冲器以响应于在交易数据存储器中变得可用的第一交易数据，向与互连相关联的仲裁器发送请求（REQ）信号，响应于授权（GNT） 从仲裁器接收到的信号，从事务缓冲器检索第二事务数据并将第二事务数据发送到互连上，并且在第二事务数据已被传输到互连之后，从事务数据存储器检索的第三事务数据重新填充事务缓冲器 。

公开(公告)号：US20230418361A1

公开(公告)日：2023-12-28

申请号：US18244748

申请日：2023-09-11

Applicant: Intel Corporation

Inventor： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US10657092B2

公开(公告)日：2020-05-19

申请号：US15199302

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Timothy J. Callahan ,  Hem Doshi ,  Hooi Kar Loo ,  Suketu U. Bhatt

IPC: G06F13/42

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing. For instance, in accordance with one embodiment, there is a functional semiconductor device, comprising: a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a transaction and issue the transaction onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to modify the transaction received to form a modified transaction; in which the virtualized device logic is to issue the modified transaction onto the device fabric; and in which the modified transaction is returned to the transaction originator. Other related embodiments are disclosed.