公开(公告)号：US10958278B2

公开(公告)日：2021-03-23

申请号：US16528435

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J. Ragland ,  Yoav Ben-Raphael ,  Ernest Knoll

IPC: H03D3/24 ,  H03L7/18 ,  H03L7/14 ,  H03L7/187

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.

公开(公告)号：US11789516B2

公开(公告)日：2023-10-17

申请号：US17440688

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC: G06F1/00 ,  G06F1/324

CPC classification number: G06F1/324

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US20230131521A1

公开(公告)日：2023-04-27

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F1/3203 ,  G06F9/50 ,  G06F1/324

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US20220179473A1

公开(公告)日：2022-06-09

申请号：US17440688

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC: G06F1/324

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US11579944B2

公开(公告)日：2023-02-14

申请号：US16190806

申请日：2018-11-14

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/50 ,  G06F9/52 ,  G06F13/20 ,  G06F1/28 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  G06F1/3287

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US10379596B2

公开(公告)日：2019-08-13

申请号：US15227040

申请日：2016-08-03

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Nir Rosenzweig ,  Efraim Rotem ,  Yoav Ben-Raphael ,  Alon Naveh

IPC: G06F1/3206 ,  G06F1/3287 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.

公开(公告)号：US20190079806A1

公开(公告)日：2019-03-14

申请号：US16190806

申请日：2018-11-14

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/52 ,  G06F13/20 ,  G06F9/50 ,  G06F1/28

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US11953962B2

公开(公告)日：2024-04-09

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/50 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/324 ,  G06F9/5044 ,  G06F9/5094 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US20230418361A1

公开(公告)日：2023-12-28

申请号：US18244748

申请日：2023-09-11

Applicant: Intel Corporation

Inventor： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US20210036708A1

公开(公告)日：2021-02-04

申请号：US16528435

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J. Ragland ,  Yoav Ben-Raphael ,  Ernest Knoll

IPC: H03L7/18 ,  H03L7/187 ,  H03L7/14

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.