公开(公告)号：US20180137005A1

公开(公告)日：2018-05-17

申请号：US15814336

申请日：2017-11-15

Applicant: Intel Corporation

Inventor： Wei Wu ,  Uksong Kang ,  Hussein Alameer ,  Rajat Agarwal ,  Kjersten E. Criss ,  John B. Halbert

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/108 ,  G11C5/063 ,  G11C7/10 ,  G11C11/40618 ,  G11C11/4093 ,  G11C29/44 ,  G11C29/52 ,  G11C29/835 ,  G11C29/846

Abstract: In a memory system a multichip memory provides data redundancy for error recovery. The multichip memory can be an integrated circuit package with multiple memory dies or memory devices integrated with a common package. The multiple memory dies are coupled in a daisy chain, and can be a vertical stack or in a planar formation. The memory chip or chips at the end of the chain store parity data, and the other devices store data. The multichip memory includes XOR (exclusive OR) logic to compute parity to store in the redundant parity chips.

公开(公告)号：US10770129B2

公开(公告)日：2020-09-08

申请号：US16106911

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Hussein Alameer ,  Kjersten Criss ,  Uksong Kang

IPC: G11C5/06 ,  G11C11/4076 ,  H01L27/02 ,  G11C5/04 ,  G06F12/08 ,  G11C11/4093

Abstract: An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.

公开(公告)号：US20190043552A1

公开(公告)日：2019-02-07

申请号：US16106911

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Hussein Alameer ,  Kjersten Criss ,  Uksong Kang

IPC: G11C11/4076 ,  H01L27/02

CPC classification number: G11C11/4076 ,  G06F12/08 ,  G11C5/04 ,  G11C5/066 ,  G11C11/4093 ,  G11C2207/105 ,  H01L27/0207

Abstract: An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.

公开(公告)号：US10459809B2

公开(公告)日：2019-10-29

申请号：US15640182

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Hussein Alameer ,  Uksong Kang ,  Kjersten E. Criss ,  Rajat Agarwal ,  Wei Wu ,  John B. Halbert

IPC: G11C5/02 ,  G06F11/16 ,  G06F11/10 ,  G11C5/04 ,  G11C7/10 ,  G11C29/42 ,  G11C29/52 ,  G11C29/00 ,  G11C7/24 ,  H01L25/065 ,  G11C29/04

Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

公开(公告)号：US11144466B2

公开(公告)日：2021-10-12

申请号：US16433663

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Jongwon Lee ,  Vivek Kozhikkottu ,  Kuljit S. Bains ,  Hussein Alameer

IPC: G06F12/0882 ,  G11C7/10

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

公开(公告)号：US20190286566A1

公开(公告)日：2019-09-19

申请号：US16433663

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Jongwon Lee ,  Vivek Kozhikkottu ,  Kuljit S. Bains ,  Hussein Alameer

IPC: G06F12/0882 ,  G11C7/10

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.