公开(公告)号：US20210191753A1

公开(公告)日：2021-06-24

申请号：US16723691

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Jacob Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F9/48 ,  G06F9/54

Abstract: Apparatus, method, and machine-readable medium to provide performance state matching between source and target processors based on inter-processor interrupts. An exemplary apparatus includes a target processor to execute a receiving task at a first performance level and a source processor to execute a sending task at a second performance level higher than the first performance level. The sending task is to store interrupt routing data indicating a pairing between the sending task and the receiving task into a memory location and that the sending task is to dispatch work to be processed by the receiving task. The apparatus further includes a performance management unit to detect the pairing between the sending task and the receiving task based on the interrupt routing data and responsively adjust the performance level of the target processor from the first performance level to the second performance level based, at least in part, on the pairing.

公开(公告)号：US11775336B2

公开(公告)日：2023-10-03

申请号：US16723691

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Jacob Pan ,  Ashok Raj ,  Srinivas Pandruvada

IPC: G06F9/48 ,  G06F9/54 ,  G06F15/163 ,  G06F15/173

CPC classification number: G06F9/4812 ,  G06F9/544 ,  G06F15/163 ,  G06F15/17325 ,  G06F2209/486

Abstract: Apparatus, method, and machine-readable medium to provide performance state matching between source and target processors based on inter-processor interrupts. An exemplary apparatus includes a target processor to execute a receiving task at a first performance level and a source processor to execute a sending task at a second performance level higher than the first performance level. The sending task is to store interrupt routing data indicating a pairing between the sending task and the receiving task into a memory location and that the sending task is to dispatch work to be processed by the receiving task. The apparatus further includes a performance management unit to detect the pairing between the sending task and the receiving task based on the interrupt routing data and responsively adjust the performance level of the target processor from the first performance level to the second performance level based, at least in part, on the pairing.