公开(公告)号：US20220208778A1

公开(公告)日：2022-06-30

申请号：US17134281

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Jason PECK ,  Uygar E. AVCI ,  Jack T. KAVALIEROS

IPC: H01L27/11514 ,  H01L27/11504 ,  H01L27/11507 ,  G11C7/18 ,  G11C8/14 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

Abstract: A memory device comprises a series of alternating plate lines and an insulating material over a substrate. Two or more ferroelectric capacitors are through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel wordlines is along a second direction orthogonal to the first direction over the two or more ferroelectric capacitors. An access transistor is located over and controls the two or more ferroelectric capacitors, the access transistor incorporating a first one of the bitlines and a first one of the wordlines. The bitline comprise a first source/drain of a source/drain pair, and a second source/drain is aligned, and in contact, with a top one of the two or more ferroelectric capacitors, and the first wordline forms a gate of the access transistor.

公开(公告)号：US20190393356A1

公开(公告)日：2019-12-26

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. LE ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Miriam RESHOTKO ,  Matthew METZ ,  Yih WANG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Tahir GHANI ,  Nazila HARATIPOUR ,  Abhishek SHARMA ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L27/108 ,  H01L23/522 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190138893A1

公开(公告)日：2019-05-09

申请号：US16147176

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20230097641A1

公开(公告)日：2023-03-30

申请号：US17485311

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Christopher M. NEUMANN ,  Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L27/11514 ,  H01L27/11504 ,  H01L21/768

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, ferroelectric three-dimensional (3D) memory architectures. Other embodiments may be disclosed or claimed.

公开(公告)号：US20210407902A1

公开(公告)日：2021-12-30

申请号：US16913859

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Mengcheng LU ,  Jitendra Kumar JHA ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Scott B. CLENDENNING ,  Eric Charles MATTSON

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US20210167182A1

公开(公告)日：2021-06-03

申请号：US16700757

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Ashish Verma PENUMATCHA ,  Sou-Chi CHANG ,  Devin MERRILL ,  I-Cheng TUNG ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Shriram SHIVARAMAN ,  Eric Charles MATTSON

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20210111179A1

公开(公告)日：2021-04-15

申请号：US16599422

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Nazila HARATIPOUR ,  Uygar E. AVCI

IPC: H01L27/11514 ,  H01L49/02 ,  H01L27/11507 ,  G11C11/22 ,  H01L27/11504

Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.

公开(公告)号：US20200312950A1

公开(公告)日：2020-10-01

申请号：US16369737

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Ashish Verma PENUMATCHA ,  Owen LOH ,  Mengcheng LU ,  Seung Hoon SUNG ,  Ian A. YOUNG ,  Uygar AVCI ,  Jack T. KAVALIEROS

IPC: H01L49/02 ,  H01L27/11585 ,  H01L23/522 ,  H01G4/30 ,  H01G4/012

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

公开(公告)号：US20230097736A1

公开(公告)日：2023-03-30

申请号：US17485308

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Uygar E. AVCI ,  Jason PECK ,  Nafees A. KABIR ,  Sarah ATANASOV

IPC: H01L27/11507 ,  G11C11/22 ,  H01L27/11504

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to ferroelectric random access memory (FRAM) devices with an enhanced capacitor architecture. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220208777A1

公开(公告)日：2022-06-30

申请号：US17134279

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Jack T. KAVALIEROS

IPC: H01L27/11514 ,  H01L23/522 ,  H01L27/11507

Abstract: A memory device comprises an access transistor comprising a bitline and a wordline. A series of alternating plate lines and an insulating material is over the access transistor, the plate lines comprising an adhesion material on a top and a bottom thereof and a metal material in between the adhesion material, the metal material having one or more voids therein. Two or more ferroelectric capacitors is over the access transistor and through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines, and wherein the two or more ferroelectric capacitors are each coupled to and controlled by the access transistor. A plurality of vias each land on a respective one of the plate lines, wherein the plurality of vias comprises a same metal material as the plate lines.