公开(公告)号：US20170289850A1

公开(公告)日：2017-10-05

申请号：US15089454

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Bill NALE ,  Pete D VOGT

IPC: H04W28/08 ,  H04W24/02 ,  H04B3/36

CPC classification number: H04W28/085 ,  H04B3/36 ,  H04W24/02

Abstract: A system includes a repeater architecture for commands where memory connects to a host for with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of command signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of command signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices, to extend the memory channel to the second group of memory devices. The memory circuit includes a repeater to share the command bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for commands to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for commands to the first group of memory devices.

公开(公告)号：US20170285992A1

公开(公告)日：2017-10-05

申请号：US15089453

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Pete D VOGT

IPC: G06F3/06

CPC classification number: G06F13/16 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4093

Abstract: A system with memory includes a repeater architecture where memory connects to a host with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second group of signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices. The second group of signal lines extends the memory channel to the second group of memory devices. The second group of signal lines includes fewer data signal lines than the first group of signal lines, to support a lower bandwidth than the first group of signal lines on the memory channel.