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    Three Dimensional Circuit Systems And Methods Having Memory Hierarchies
    2.
    发明申请
    Three Dimensional Circuit Systems And Methods Having Memory Hierarchies 有权

    公开(公告)号：US20220405005A1

    公开(公告)日：2022-12-22

    申请号：US17349592

    申请日：2021-06-16

    Applicant: Intel Corporation

    Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

    IPC: G06F3/06

    Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

    Data storage for accelerating functions
    3.
    发明授权
    Data storage for accelerating functions 有权

    公开(公告)号：US11237757B2

    公开(公告)日：2022-02-01

    申请号：US15645951

    申请日：2017-07-10

    Applicant: Intel Corporation

    Inventor： Ravi Gutala ,  Aravind Dasu

    IPC: G06F3/06 ,  H03K19/00 ,  G06F15/76 ,  G06F30/00

    Abstract: An integrated circuit package includes a memory integrated circuit die and a coprocessor integrated circuit die that is coupled to the memory integrated circuit die. The coprocessor integrated circuit die has a logic sector that is configured to accelerate a function for a host processor. The logic sector generates an intermediate result of a computation performed as part of the function. The intermediate result is transmitted to and stored in the memory integrated circuit die.

    Techniques for fluid cooling of integrated circuits in packages
    4.
    发明授权
    Techniques for fluid cooling of integrated circuits in packages 有权

    公开(公告)号：US10964624B2

    公开(公告)日：2021-03-30

    申请号：US15416589

    申请日：2017-01-26

    Applicant: Intel Corporation

    Inventor： Ravi Gutala ,  Aravind Dasu

    IPC: H01L23/473 ,  H01L25/065 ,  G11C7/04 ,  H05K7/20 ,  H01L23/00

    Abstract: A method is provided for removing heat from an integrated circuit package. Fluid coolant is provided from a fluid inlet of a fluid routing device through channels in the fluid routing device to absorb heat generated by first and second integrated circuit dies in the integrated circuit package. The fluid routing device is mounted on a surface of each of the first and second integrated circuit dies. The fluid coolant is provided from the channels to a fluid outlet of the fluid routing device. A flow of the fluid coolant through the fluid routing device is adjusted to reduce a temperature of the first integrated circuit die in response to an increase in a workload of the first integrated circuit die.

    Three dimensional programmable logic circuit systems and methods
    5.
    发明授权
    Three dimensional programmable logic circuit systems and methods 有权

    公开(公告)号：US11489527B2

    公开(公告)日：2022-11-01

    申请号：US17354473

    申请日：2021-06-22

    Applicant: Intel Corporation

    Inventor： Scott Weber ,  Aravind Dasu ,  Ravi Gutala ,  Mahesh Iyer ,  Eriko Nurvitadhi ,  Archanna Srinivasan ,  Sean Atsatt ,  James Ball

    IPC: H03K19/17736 ,  H01L25/18 ,  H03K19/17768 ,  H03K19/1776

    Abstract: A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.

    Systems And Methods For Circuit Design Dependent Programmable Maximum Junction Temperatures
    6.
    发明申请
    Systems And Methods For Circuit Design Dependent Programmable Maximum Junction Temperatures 有权

    公开(公告)号：US20220004688A1

    公开(公告)日：2022-01-06

    申请号：US17481038

    申请日：2021-09-21

    Applicant: Intel Corporation

    Inventor： Archanna Srinivasan ,  Rajiv Mongia ,  Ravi Gutala ,  Kaushik Chanda ,  Gurvinder Tiwana ,  Vadali Mahadev ,  Mahesh A. Iyer

    IPC: G06F30/337 ,  G06F30/343

    Abstract: Systems and methods are provided for generating a circuit design for an integrated circuit using a circuit design tool. The circuit design tool determines maximum junction temperatures for circuit blocks in the circuit design for the integrated circuit. The circuit design tool determines defects values for the circuit blocks using the maximum junction temperatures for the circuit blocks. The circuit design tool determines a defects value for the circuit design based on the defects values for the circuit blocks. The circuit design tool determines a maximum junction temperature for the circuit design based on a comparison between the defects value for the circuit design and a target defects value for the circuit design. The circuit design tool can dynamically reconfigure configurable logic circuit blocks to improve the power, the performance, and the thermal profile to achieve an optimal junction temperature per circuit block.

    Voltage Regulator Circuit Systems And Methods
    7.
    发明申请
    Voltage Regulator Circuit Systems And Methods 有权

    公开(公告)号：US20210311517A1

    公开(公告)日：2021-10-07

    申请号：US17352194

    申请日：2021-06-18

    Applicant: Intel Corporation

    Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

    IPC: G05F1/575 ,  G05F1/577

    Abstract: A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.

    Data Storage For Accelerating Functions
    8.
    发明申请
    Data Storage For Accelerating Functions 审中-公开

    公开(公告)号：US20190012116A1

    公开(公告)日：2019-01-10

    申请号：US15645951

    申请日：2017-07-10

    Applicant: Intel Corporation

    Inventor： Ravi Gutala ,  Aravind Dasu

    IPC: G06F3/06

    Abstract: An integrated circuit package includes a memory integrated circuit die and a coprocessor integrated circuit die that is coupled to the memory integrated circuit die. The coprocessor integrated circuit die has a logic sector that is configured to accelerate a function for a host processor. The logic sector generates an intermediate result of a computation performed as part of the function. The intermediate result is transmitted to and stored in the memory integrated circuit die.

    Voltage regulator circuit systems and methods
    9.
    发明授权
    Voltage regulator circuit systems and methods 有权

    公开(公告)号：US12253870B2

    公开(公告)日：2025-03-18

    申请号：US17352194

    申请日：2021-06-18

    Applicant: Intel Corporation

    Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

    IPC: G05F1/575 ,  G05F1/577 ,  H01L25/065 ,  H03K19/00

    Abstract: A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.

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