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公开(公告)号：US10333379B2
公开(公告)日：2019-06-25
申请号：US15382076
申请日：2016-12-16
Applicant: Intel Corporation
Inventor： Suphachai Chai Sutanthavibul , Iqbal Rajwani , Anupama A Thaploo , Surya Sasi Kiran Tallapragada , Daivik H Bhatt , Lei Jiang , Stephen Kim , Pascal A. Meinerzhagen , Muhammad M. Khellah
IPC: H02M1/08 , H03K17/0812 , H03K17/687 , H02M3/158 , H02M1/088 , H03K19/00 , H02M1/00 , H03K17/08
Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.
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公开(公告)号：US12184751B2
公开(公告)日：2024-12-31
申请号：US17341150
申请日：2021-06-07
Applicant: Intel Corporation
Inventor： Sandipan Kundu , Ajay Balankutty , Bong Chan Kim , Yutao Liu , Jihwan Kim , Kai Yu , Gurmukh Singh , Stephen Kim , Richard Packard , Frank O'Mahony
Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.
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公开(公告)号：US10908673B2
公开(公告)日：2021-02-02
申请号：US15891081
申请日：2018-02-07
Applicant: Intel Corporation
Inventor： Pascal Meinerzhagen , Stephen Kim , Dongmin Yoon , Minki Cho , Muhammad Khellah
IPC: G06F1/32 , G05F1/563 , G05F1/59 , G06F1/3296 , G06F1/3287 , G06F1/3234 , G06F1/324
Abstract: An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.
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Patent Agency Ranking
公开(公告)号：US20190243440A1
公开(公告)日：2019-08-08
申请号：US15891081
申请日：2018-02-07
Applicant: Intel Corporation
Inventor： Pascal Meinerzhagen , Stephen Kim , Dongmin Yoon , Minki Cho , Muhammad Khellah
CPC classification number: G06F1/3296 , G05F1/563 , G05F1/59 , G06F1/324 , G06F1/3243 , G06F1/3287
Abstract: An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.
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公开(公告)号：US20220200781A1
公开(公告)日：2022-06-23
申请号：US17341150
申请日：2021-06-07
Applicant: Intel Corporation
Inventor： Sandipan Kundu , Ajay Balankutty , Bong Chan Kim , Yutao Liu , Jihwan Kim , Kai Yu , Gurmukh Singh , Stephen Kim , Richard Packard , Frank O'Mahony
Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.
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公开(公告)号：US10108212B2
公开(公告)日：2018-10-23
申请号：US14861997
申请日：2015-09-22
Applicant: Intel Corporation
Inventor： Sunghyun Park , Stephen Kim , Krishnan Ravichandran , Sriram R. Vangal , Vivek K. De
Abstract: Some embodiments include apparatuses and methods having a power switching unit to receive a first voltage and provide a second voltage having a value based on a value of the first voltage, a first loop to provide digital control information to control a switching of the power switching unit in order to maintain a relationship between the value of the second voltage and a value of a reference voltage, and a second loop coupled to the power switching unit and the first loop to calculate a value of energy consumption of at least a portion of the apparatus based at least on the digital control information.
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7.发明授权公开(公告)号：US12111786B2
公开(公告)日：2024-10-08
申请号：US17338512
申请日：2021-06-03
Applicant: Intel Corporation
Inventor： Jihwan Kim , Ajay Balankutty , Sandipan Kundu , Stephen Kim , Frank O'Mahony , Kai Yu , Bong Chan Kim
IPC: G06F13/42 , G06F1/06 , G06F1/10 , H03K17/687 , H03L7/00
CPC classification number: G06F13/4291 , G06F1/06 , G06F1/10 , H03K17/6872 , H03K17/6874 , H03L7/00
Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.
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8.发明申请公开(公告)号：US20220147482A1
公开(公告)日：2022-05-12
申请号：US17338512
申请日：2021-06-03
Applicant: Intel Corporation
Inventor： Jihwan Kim , Ajay Balankutty , Sandipan Kundu , Stephen Kim , Frank O'Mahony , Kai Yu , Bong Chan Kim
IPC: G06F13/42 , H03K17/687 , G06F1/10 , G06F1/06
Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.
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