公开(公告)号：US09990016B2

公开(公告)日：2018-06-05

申请号：US15674594

申请日：2017-08-11

Applicant: Intel Corporation

Inventor： Thanunathan Rangarajan ,  Vinayak P. Risbud ,  Tabassum Yasmin

IPC: G06F12/00 ,  G06F1/20 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/00 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F1/206 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/04 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/0409 ,  Y02D10/16

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

公开(公告)号：US20240192755A1

公开(公告)日：2024-06-13

申请号：US18077131

申请日：2022-12-07

Applicant: Intel Corporation

Inventor： Chuen Ming Tan ,  Venkataramani Gopalakrishnan ,  Aneesh Tuljapurkar ,  Vishwanath Somayaji ,  Tabassum Yasmin

IPC: G06F1/3225 ,  G06F1/3287

CPC classification number: G06F1/3225 ,  G06F1/3287

Abstract: Embodiments herein relate to a circuit which allows the re-use of an existing power supply units having main power rails and an auxiliary power rail, while supporting large memory configurations in a sleep state to avoid data loss. A processor determines whether a power requirement of memory modules in a computing device exceeds an available power of the auxiliary power rail. If this is the case, the processor asserts an override signal which is used by a logic circuit to force the power supply to remain on in the sleep state. A set of switches disconnect the main rails from other components which can be turned off in the sleep state. A select circuit selects one of the main rails to power the memory modules.

公开(公告)号：US20160048347A1

公开(公告)日：2016-02-18

申请号：US14460533

申请日：2014-08-15

Applicant: Intel Corporation

Inventor： Thanunathan Rangarajan ,  Vinayak P. Risbud ,  Tabassum Yasmin

IPC: G06F3/06

CPC classification number: G06F1/206 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/04 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/0409 ,  Y02D10/16

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的至少一个核和耦合到所述至少一个核的存储器控​​制器。 反过来，存储器控制器包括备用逻辑，用于响应于第一存储器件的温度超过热阈值，将存储在耦合到处理器的第一存储器件上的数据的动态传输耦合到耦合到处理器的第二存储器件 。 描述和要求保护其他实施例。

公开(公告)号：US20170351308A1

公开(公告)日：2017-12-07

申请号：US15674594

申请日：2017-08-11

Applicant: Intel Corporation

Inventor： Thanunathan Rangarajan ,  Vinayak P. Risbud ,  Tabassum Yasmin

IPC: G06F1/20 ,  G11C7/04 ,  G11C29/00 ,  G11C29/46 ,  G11C29/20 ,  G11C29/04 ,  G11C5/04

CPC classification number: G06F1/206 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/04 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/0409 ,  Y02D10/16

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

公开(公告)号：US09760136B2

公开(公告)日：2017-09-12

申请号：US14460533

申请日：2014-08-15

Applicant: Intel Corporation

Inventor： Thanunathan Rangarajan ,  Vinayak P. Risbud ,  Tabassum Yasmin

IPC: G06F12/00 ,  G06F1/20 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/00 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F1/206 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/04 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/0409 ,  Y02D10/16

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.