公开(公告)号：US11432421B2

公开(公告)日：2022-08-30

申请号：US16847106

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Samarth Alva ,  Krishnakumar Varadarajan ,  Yogesh Channaiah ,  Prakash Pillai ,  Sagar Pawar ,  Aneesh Tuljapurkar ,  Raghavendra N

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  H05K5/02 ,  G06K7/10 ,  H01F7/02

Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.

公开(公告)号：US10653026B2

公开(公告)日：2020-05-12

申请号：US15864583

申请日：2018-01-08

Applicant: Intel Corporation

Inventor： Samarth Alva ,  Krishnakumar Varadarajan ,  Yogesh Channaiah ,  Prakash Pillai ,  Sagar Pawar ,  Aneesh Tuljapurkar ,  Raghavendra N

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  H05K5/02 ,  G06K7/10 ,  H01F7/02

Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.

公开(公告)号：US20210373833A1

公开(公告)日：2021-12-02

申请号：US16890798

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Sagar Pawar ,  Prakash Pillai ,  Ovais Pir ,  Murali Iyengar ,  Pannerkumar Rajagopal ,  Raghavendra N ,  Aneesh Tuljapurkar

IPC: G06F3/14 ,  G06F3/0487 ,  G09G3/34

Abstract: Techniques and mechanisms for power management of display devices based on an indication that a user exhibits interest in one, but not all, of said display devices. In an embodiment, logic of a computer device identifies a condition wherein a user of the computer device exhibits insufficient interest in a first display device, while exhibiting at least some interest user in a second display device. The first display device and the second display device support an extended display mode of an operating system. Based on the condition, the logic automatically reduces a consumption of power by the first display device. Of the first display device and the second display device, only the first display device is subjected to a power state transition based on the condition.

公开(公告)号：US20200245483A1

公开(公告)日：2020-07-30

申请号：US16847106

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Samarth Alva ,  Krishnakumar Varadarajan ,  Yogesh Channaiah ,  Prakash Pillai ,  Sagar Pawar ,  Aneesh Tuljapurkar ,  Raghavendra N.

IPC: H05K5/02 ,  H01F7/02 ,  G06F1/16 ,  G06K7/10

Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.

公开(公告)号：US20240192755A1

公开(公告)日：2024-06-13

申请号：US18077131

申请日：2022-12-07

Applicant: Intel Corporation

Inventor： Chuen Ming Tan ,  Venkataramani Gopalakrishnan ,  Aneesh Tuljapurkar ,  Vishwanath Somayaji ,  Tabassum Yasmin

IPC: G06F1/3225 ,  G06F1/3287

CPC classification number: G06F1/3225 ,  G06F1/3287

Abstract: Embodiments herein relate to a circuit which allows the re-use of an existing power supply units having main power rails and an auxiliary power rail, while supporting large memory configurations in a sleep state to avoid data loss. A processor determines whether a power requirement of memory modules in a computing device exceeds an available power of the auxiliary power rail. If this is the case, the processor asserts an override signal which is used by a logic circuit to force the power supply to remain on in the sleep state. A set of switches disconnect the main rails from other components which can be turned off in the sleep state. A select circuit selects one of the main rails to power the memory modules.