公开(公告)号：US20190341305A1

公开(公告)日：2019-11-07

申请号：US16387469

申请日：2019-04-17

Applicant: INVENSENSE, INC.

Inventor： Bongsang KIM ,  Joe SEEGER

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/8238

Abstract: Selectively controlling application of a self-assembled monolayer (SAM) coating on a substrate of a device is presented herein. A method comprises: forming a material on a first substrate; removing a selected portion of the material from a defined contact area of the first substrate; forming a SAM coating on the material and the defined contact area—the SAM coating comprising a first adhesion force with respect to the material and a second adhesion force with respect to the defined contact area, and the first adhesion force being less than the second adhesion force; removing the SAM coating that has been formed on the material; and attaching the first substrate to the second substrate—the first substrate being positioned across from the second substrate, and the SAM coating that has been formed on the defined contact area being positioned across from a bump stop of the second substrate.

公开(公告)号：US20190035905A1

公开(公告)日：2019-01-31

申请号：US16044233

申请日：2018-07-24

Applicant: InvenSense, Inc.

Inventor： Bongsang KIM ,  Jongwoo SHIN ,  Joseph SEEGER ,  Logeeswaran Veerayah JAYARAMAN ,  Houri JOHARI-GALLE

IPC: H01L29/49 ,  G01P15/097 ,  H01L23/532

Abstract: A method includes depositing a silicon layer over a first oxide layer that overlays a first silicon substrate. The method further includes depositing a second oxide layer over the silicon layer to form a composite substrate. The composite substrate is bonded to a second silicon substrate to form a micro-electro-mechanical system (MEMS) substrate. Holes within the second silicon substrate are formed by reaching the second oxide layer of the composite substrate. The method further includes removing a portion of the second oxide layer through the holes to release MEMS features. The MEMS substrate may be bonded to a CMOS substrate.

公开(公告)号：US20200131031A1

公开(公告)日：2020-04-30

申请号：US16440860

申请日：2019-06-13

Applicant: InvenSense, Inc.

Inventor： Daesung LEE ,  Dongyang KANG ,  Chienlu CHANG ,  Bongsang KIM ,  Alan CUTHBERTSON

IPC: B81B7/02 ,  B81C1/00 ,  B81C3/00

Abstract: Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. A hardmask is deposited on a second side of the device wafer, wherein the second side is planar. The hardmask is etched to form a MEMS device pattern and a standoff pattern. Standoffs are formed on the device wafer, wherein the standoffs are defined by the standoff pattern. A eutectic bond metal is deposited on the standoffs, the device wafer, and the hardmask. A first photoresist is deposited and removed, such that the first photoresist covers the standoffs. The eutectic bond metal is etched using the first photoresist. The MEMS device pattern is etched into the device wafer. The first photoresist and the hardmask are removed.

公开(公告)号：US20190241432A1

公开(公告)日：2019-08-08

申请号：US16389472

申请日：2019-04-19

Applicant: InvenSense, Inc.

Inventor： Jong Il SHIN ,  Peter SMEYS ,  Bongsang KIM

IPC: B81C1/00 ,  B81B3/00

Abstract: Provided herein is an apparatus including a cavity in a first side of a first silicon wafer, and an oxide layer on the first side and in the cavity. A first side of a second silicon wafer is bonded to the first side of the first silicon wafer. A gap control structure is on a second side of the second silicon wafer, and a MEMS structure in the second silicon wafer. A eutectic bond is bonding the second side of the second silicon wafer to a third silicon wafer. A lower cavity is between the second side of the silicon wafer and the third silicon wafer, wherein the gap control structure is outside of the lower cavity and the eutectic bond.

公开(公告)号：US20170297911A1

公开(公告)日：2017-10-19

申请号：US15298499

申请日：2016-10-20

Applicant: InvenSense, Inc.

Inventor： Jong II SHIN ,  Peter SMEYS ,  Bongsang KIM

IPC: B81C1/00 ,  B81B3/00 ,  B81B7/02

CPC classification number: B81C1/00682 ,  B81B3/0078 ,  B81B7/02 ,  B81C1/00333 ,  B81C2203/0118 ,  B81C2203/036

Abstract: Provided herein is a method including forming a cavity in a first side of a first silicon wafer. An oxide layer is formed on the first side and in the cavity. The first side of the first silicon wafer is bonded to a first side of a second silicon wafer, and a gap control structure is deposited on a second side of the second silicon wafer. A MEMS structure is formed in the second silicon wafer. The second side of the second silicon wafer is eutecticly bonded to the third silicon wafer, and the eutectic bonding includes pressing the second silicon wafer to the third silicon wafer.