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    Correction die for wafer/die stack
    4.
    发明授权
    Correction die for wafer/die stack 有权

    公开(公告)号：US11605614B2

    公开(公告)日：2023-03-14

    申请号：US16823391

    申请日：2020-03-19

    Applicant: Invensas LLC

    Inventor： Belgacem Haba

    IPC: H01L21/78 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66

    Abstract: Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.

    CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES
    5.
    发明申请
    CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES 有权

    公开(公告)号：US20230040454A1

    公开(公告)日：2023-02-09

    申请号：US17959585

    申请日：2022-10-04

    Applicant: Invensas LLC

    Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

    IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/311 ,  H01L21/02 ,  H01L23/64

    Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

    STACKED STRUCTURE WITH INTERPOSER
    6.
    发明申请
    STACKED STRUCTURE WITH INTERPOSER 有权

    公开(公告)号：US20230069183A1

    公开(公告)日：2023-03-02

    申请号：US17823430

    申请日：2022-08-30

    Applicant: INVENSAS LLC

    Inventor： Belgacem Haba

    IPC: H01L23/40 ,  H01L23/485 ,  H01L25/065

    Abstract: Stacked structures having interposers adhered to packaging substrates are disclosed. In one example, a stacked structure can include a laminate substrate. The stacked structure can also include an interposer mounted on the laminate substrate without solder, for example by an electrically nonconductive adhesive layer. A plurality of conductive vias can be extending through the interposer, and through the nonconductive adhesive layer if present, and connecting to the laminate substrate. The stacked structure can also include a redistribution layer (RDL) adjacent to the interposer. The RDL can be configured to electrically connect to an electronic device. Methods for forming such stacked structures are also disclosed.

    Capacitive coupling in a direct-bonded interface for microelectronic devices
    7.
    发明授权
    Capacitive coupling in a direct-bonded interface for microelectronic devices 有权

    公开(公告)号：US11495579B2

    公开(公告)日：2022-11-08

    申请号：US17074401

    申请日：2020-10-19

    Applicant: Invensas LLC

    Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

    IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/311 ,  H01L21/02 ,  H01L23/64

    Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

    Connecting multiple chips using an interconnect device
    8.
    发明授权
    Connecting multiple chips using an interconnect device 有权

    公开(公告)号：US12154858B2

    公开(公告)日：2024-11-26

    申请号：US16905766

    申请日：2020-06-18

    Applicant: Invensas LLC

    Inventor： Javier A. Delacruz ,  Belgacem Haba

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10

    Abstract: Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip.

    RADIO FREQUENCY DEVICE PACKAGES
    9.
    发明申请
    RADIO FREQUENCY DEVICE PACKAGES 有权

    公开(公告)号：US20230130259A1

    公开(公告)日：2023-04-27

    申请号：US18048378

    申请日：2022-10-20

    Applicant: INVENSAS LLC

    Inventor： Belgacem Haba ,  Hong Shen ,  Patrick Variot ,  Rajesh Katkar

    IPC: H01Q9/04 ,  H01Q1/52 ,  H01Q1/48 ,  H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

    Abstract: An integrated device package is disclosed. The integrated device package can include an antenna structure and an integrated device die electrically coupled to the antenna structure. The antenna structure can be formed with a system board or separated from the system board. When the antenna structure is formed with the system board, the integrated device package can include a redistribution layer having conductive routing traces such that the integrated device die is disposed between the system board and the redistribution layer, and the integrated device die is electrically coupled to the antenna structure at least partially through one or more of the conductive routing traces of the redistribution layer. When the antenna structure is separated from the system board, the integrated device die can be positioned between the antenna structure and the system board, and the integrated device die can be electrically coupled to the antenna structure at least partially through one or more of conductive routing traces of the system board and conductive wire of an interconnect structure between the system board and the antenna structure.

    Nanowire bonding interconnect for fine-pitch microelectronics
    10.
    发明授权
    Nanowire bonding interconnect for fine-pitch microelectronics 有权

    公开(公告)号：US11387202B2

    公开(公告)日：2022-07-12

    申请号：US16776182

    申请日：2020-01-29

    Applicant: INVENSAS LLC

    Inventor： Belgacem Haba ,  Ilyas Mohammed

    IPC: H01L23/00

    Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 μm from each other to enable contact or direct-bonding between pads and vias with diameters under 5 μm at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 μm in height for direct bonding.

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