公开(公告)号：US11621126B2

公开(公告)日：2023-04-04

申请号：US17467841

申请日：2021-09-07

Applicant: KEMET Electronics Corporation

Inventor： John Bultitude ,  Nathan A. Reed ,  Allen Templeton ,  James R. Magee ,  James Davis ,  Abhijit Gurav ,  Hunter Hayes ,  Hanzheng Guo

IPC: H01G4/12 ,  C04B35/465 ,  H01G4/30 ,  C04B35/50 ,  C04B35/495 ,  H01G4/40

Abstract: Provided is an improved multilayered ceramic capacitor and an electronic device comprising the multilayered ceramic capacitor. The multilayer ceramic capacitor comprises first conductive plates electrically connected to first external terminations and second conductive plates electrically connected to second external terminations. The first conductive plates and second conductive plates form a capacitive couple. A ceramic portion is between the first conductive plates and said second conductive plates wherein the ceramic portion comprises paraelectric ceramic dielectric. The multilayer ceramic capacitor has a rated DC voltage and a rated AC VPP wherein the rated AC VPP is higher than the rated DC voltage.

公开(公告)号：US12249463B2

公开(公告)日：2025-03-11

申请号：US17233796

申请日：2021-04-19

Applicant: KEMET Electronics Corporation

Inventor： Mark R. Laps ,  John Bultitude ,  Philip M. Lessner ,  Lonnie G. Jones ,  Allen Templeton ,  Nathan A. Reed

IPC: H01G4/258 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H01G4/38

Abstract: Provided is a heat dissipating capacitor comprising internal electrodes of opposing polarity forming a capacitive couple between external terminations. A dielectric is between the internal electrodes. The heat dissipating capacitor comprises at least one thermal dissipation layer and at least one thermal conductive termination wherein the thermal dissipation layer is in thermally conductive contact with the thermal conductive termination.

公开(公告)号：US20230038175A1

公开(公告)日：2023-02-09

申请号：US17968567

申请日：2022-10-18

Applicant: KEMET Electronics Corporation

Inventor： John E. McConnell ,  John Bultitude ,  Allen Templeton

IPC: H01G2/08 ,  H05K7/20 ,  H05K1/02

Abstract: Provided is an electronic module comprising at least one electronic component. A thermoelectric cooler is in thermal contact with the electronic component. A temperature controller is capable of determining a device temperature of the electronic component is provided and capable of providing current to the thermoelectric cooler proportional to a deviation of the device temperature from an optimal temperature range.

公开(公告)号：US10950688B2

公开(公告)日：2021-03-16

申请号：US16531255

申请日：2019-08-05

Applicant: KEMET Electronics Corporation

Inventor： John Bultitude ,  Lonnie G. Jones ,  Allen Templeton ,  Philip M. Lessner

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/48

Abstract: Provided herein is a module for packaging semiconductors comprising: at least one PDC comprising parallel internal electrodes of alternating polarity with a paraelectric dielectric between adjacent internal electrodes wherein the paraelectric dielectric has a permittivity above 10 to no more than 300; and wherein the PDC forms a capacitor couple with at least one semiconductor.

公开(公告)号：US11744018B2

公开(公告)日：2023-08-29

申请号：US17147908

申请日：2021-01-13

Applicant: KEMET Electronics Corporation

Inventor： John Bultitude ,  Peter Alexandre Blais ,  James A. Burk ,  Galen W. Miller ,  Hunter Hayes ,  Allen Templeton ,  Lonnie G. Jones ,  Mark R. Laps

IPC: H05K1/18 ,  H01G4/38 ,  H05K1/14 ,  H05K1/02 ,  H05K3/32 ,  H01L29/20 ,  H01G4/30 ,  H01L25/07 ,  H01L29/16

CPC classification number: H05K1/181 ,  H01G4/38 ,  H05K1/0272 ,  H05K1/145 ,  H05K3/328 ,  H01G4/30 ,  H01L25/072 ,  H01L29/1608 ,  H01L29/2003 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10545

Abstract: Provided is a high-density multi-component package comprising a first module interconnect pad and a second module interconnect pad. At least two electronic components are mounted to and between the first module interconnect pad and the second module interconnect pad wherein a first electronic component is vertically oriented relative to the first module interconnect pad. A second electronic component is vertically oriented relative to the second module interconnect pad.

公开(公告)号：US20230187134A1

公开(公告)日：2023-06-15

申请号：US18107154

申请日：2023-02-08

Applicant: KEMET Electronics Corporation

Inventor： John Bultitude ,  Nathan A. Reed ,  Allen Templeton ,  James R. Magee ,  James Davis ,  Abhijit Gurav ,  Hunter Hayes

IPC: H01G4/12 ,  H01G4/30 ,  C04B35/50 ,  C04B35/495 ,  C04B35/465 ,  H01G4/40

CPC classification number: H01G4/1245 ,  H01G4/306 ,  C04B35/50 ,  C04B35/495 ,  C04B35/465 ,  H01G4/1227 ,  H01G4/30 ,  H01G4/40 ,  C04B2235/66

Abstract: Provided is an improved multilayered ceramic capacitor and an electronic device comprising the multilayered ceramic capacitor. The multilayer ceramic capacitor comprises first conductive plates electrically connected to first external terminations and second conductive plates electrically connected to second external terminations. The first conductive plates and second conductive plates form a capacitive couple. A ceramic portion is between the first conductive plates and said second conductive plates wherein the ceramic portion comprises paraelectric ceramic dielectric. The multilayer ceramic capacitor has a rated DC voltage and a rated AC VPP wherein the rated AC VPP is higher than the rated DC voltage.

公开(公告)号：US20210227693A1

公开(公告)日：2021-07-22

申请号：US17147908

申请日：2021-01-13

Applicant: KEMET Electronics Corporation

Inventor： John Bultitude ,  Peter Alexandre Blais ,  James A. Burk ,  Galen W. Miller ,  Hunter Hayes ,  Allen Templeton ,  Lonnie G. Jones ,  Mark R. Laps

IPC: H05K1/18 ,  H01G4/38 ,  H05K1/14 ,  H05K1/02 ,  H05K3/32

Abstract: Provided is a high-density multi-component package comprising a first module interconnect pad and a second module interconnect pad. At least two electronic components are mounted to and between the first module interconnect pad and the second module interconnect pad wherein a first electronic component is vertically oriented relative to the first module interconnect pad. A second electronic component is vertically oriented relative to the second module interconnect pad.

公开(公告)号：US20220076892A1

公开(公告)日：2022-03-10

申请号：US17467841

申请日：2021-09-07

Applicant: KEMET Electronics Corporation

Inventor： John Bultitude ,  Nathan A. Reed ,  Allen Templeton ,  James R. Magee ,  James Davis ,  Abhijit Gurav ,  Hunter Hayes ,  Hanzheng Guo

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/40 ,  C04B35/465

Abstract: Provided is an improved multilayered ceramic capacitor and an electronic device comprising the multilayered ceramic capacitor. The multilayer ceramic capacitor comprises first conductive plates electrically connected to first external terminations and second conductive plates electrically connected to second external terminations. The first conductive plates and second conductive plates form a capacitive couple. A ceramic portion is between the first conductive plates and said second conductive plates wherein the ceramic portion comprises paraelectric ceramic dielectric. The multilayer ceramic capacitor has a rated DC voltage and a rated AC VPP wherein the rated AC VPP is higher than the rated DC voltage.

公开(公告)号：US11037871B2

公开(公告)日：2021-06-15

申请号：US16553395

申请日：2019-08-28

Applicant: KEMET Electronics Corporation

Inventor： Allen Templeton ,  John Bultitude ,  Lonnie G. Jones ,  Philip M. Lessner

IPC: H01L23/498 ,  H01L23/522 ,  H01L29/778 ,  H01L23/367

Abstract: An improved electronic assembly is provided. The electronic assembly comprises a ceramic interposer comprising multiple layers. The active layers of the multiple layers form an embedded capacitor comprising parallel electrodes with a dielectric between adjacent electrodes wherein adjacent electrodes have opposite polarity. A wide band gap device is also on the multilayered ceramic interposer.

公开(公告)号：US20200273949A1

公开(公告)日：2020-08-27

申请号：US16531255

申请日：2019-08-05

Applicant: KEMET Electronics Corporation

Inventor： John Bultitude ,  Lonnie G. Jones ,  Allen Templeton ,  Philip M. Lessner

IPC: H01L49/02 ,  H01L23/48 ,  H01L23/522

Abstract: Provided herein is a module for packaging semiconductors comprising: at least one PDC comprising parallel internal electrodes of alternating polarity with a paraelectric dielectric between adjacent internal electrodes wherein the paraelectric dielectric has a permittivity above 10 to no more than 300; and wherein the PDC forms a capacitor couple with at least one semiconductor.