公开(公告)号：US20230209713A1

公开(公告)日：2023-06-29

申请号：US17672330

申请日：2022-02-15

Applicant: KINPO ELECTRONICS, INC.

Inventor： Chuan-Wang CHANG ,  Yu-Ta LIN ,  Chen-Jung CHEN

IPC: H05K1/11 ,  H01L23/49 ,  H01L23/00

CPC classification number: H05K1/119 ,  H01L23/49 ,  H01L24/49 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2224/49173 ,  H05K2201/09027 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/0939 ,  H05K2201/094

Abstract: A pad arranging method and a pad arrangement structure for a wire bonding of a chip is provided. The method includes following steps. A soldered component and a circuit board are provided. A plurality of pads is arranged on the circuit board. a number of the pads is corresponding to a number of a plurality pins of the soldered component. The pads are disposed in a plurality of rows toward or away from the soldered component according to a predetermined arranging position, and the number of the pads on one of the rows at outer side is equal to that on one of the rows at inner side, or greater than that on one of the rows at inner side by one or more than one