公开(公告)号：US20140191396A1

公开(公告)日：2014-07-10

申请号：US14205880

申请日：2014-03-12

Applicant: MEDIA TEK INC.

Inventor： Tzu-Hung LIN ,  Wen-Sung HSU ,  Ta-Jen YU ,  Andrew C. CHANG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/48 ,  H01L23/49541 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L28/00 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/3224 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace.

Abstract translation: 在一种配置中，半导体封装包括嵌入在基底中的导电迹线和通过导电结构安装在导电迹线上的半导体器件，其中导电结构是凸块结构，并且凸块结构的宽度大于 导电迹线。 在另一种结构中，制造半导体封装的方法包括提供基底，在基底上形成至少一个导电迹线，在基底上形成额外的绝缘材料，并在附加绝缘材料上限定图案，其中图案形成在 至少一个导电迹线，其中所述导电结构是凸块结构，并且所述凸块结构的宽度大于所述导电迹线的宽度。

公开(公告)号：US20140035095A1

公开(公告)日：2014-02-06

申请号：US13721983

申请日：2012-12-20

Applicant: MEDIA TEK INC.

Inventor： Tzu-Hung LIN ,  Wen-Sung HSU ,  Ta-Jen YU ,  Andrew C. CHANG

IPC: H01L49/02 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/48 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L28/00 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2924/12042 ,  Y10T29/41 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.