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    TEMPERATURE SENSOR MANAGEMENT DURING ERROR HANDLING OPERATIONS IN A MEMORY SUB-SYSTEM
    1.
    发明申请
    TEMPERATURE SENSOR MANAGEMENT DURING ERROR HANDLING OPERATIONS IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20240385926A1

    公开(公告)日：2024-11-21

    申请号：US18661526

    申请日：2024-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Steven Michael Kientz ,  Hyungseok Kim ,  Zixiang Loh ,  Patrick R. Khayat ,  Jun Wan

    IPC: G06F11/10 ,  G11C7/04

    Abstract: A system having a processing device operatively coupled with a memory device to perform the following operations: responsive to detecting a triggering event, measuring a temperature of the memory device to obtain a suspend temperature value, enabling a suspend temperature flag to indicate that temperature input for a step of an error handling operation is based on the suspend temperature value. Updating an operating temperature with the suspend temperature value. Determining, using a data structure which maps temperatures to read level offsets, a read level offset for the step of the error handling operation, based on the operating temperature. Causing the step of the error handling operation to be performed on a set of cells using a read level value based on the read level offset and a base read level, an disabling the suspend temperature flag.

    DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICES
    3.
    发明公开
    DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICES 审中-公开

    公开(公告)号：US20240071440A1

    公开(公告)日：2024-02-29

    申请号：US17897438

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Robert W. Mason ,  Pitamber Shukla ,  Steven Michael Kientz

    IPC: G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/222

    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including periodically, at a predefined frequency, incrementing a value stored in an accumulator by a composite parameter value; responsive to receiving a program request specifying a data item to be programmed to a management unit of the memory device, obtaining a first value from the accumulator; storing the first value to a program reference table; programming the data item to the management unit; responsive to receiving a read request specifying the management unit, obtaining a second value from the accumulator; determining a read voltage value based on a difference of the first value and the second value; and performing a read operation, using the read voltage value, on the management unit.

    Trim value loading management in a memory sub-system
    4.
    发明授权
    Trim value loading management in a memory sub-system 有权

    公开(公告)号：US11914890B2

    公开(公告)日：2024-02-27

    申请号：US18168300

    申请日：2023-02-13

    Applicant: Micron Technology, Inc.

    Inventor： Steven Michael Kientz ,  Vamsi Pavan Rayaprolu

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0625 ,  G06F3/0679

    Abstract: A memory sub-system to, in response to a power up, executing a first loading process to load a sequence of a set of trim values into one or more registers of the memory sub-system. In response to a request to execute a memory access operation, interrupting the first loading process. A second loading process including loading a portion of the set of trim values corresponding to the request is executed. The memory access operation is executed using the portion of the set of trim values loaded into the one or more registers during the second loading process. Following execution of the memory access operation, the first loading process is resumed to load one or more unloaded trim values of the sequence of trim values.

    DIE FAMILY MANAGEMENT ON A MEMORY DEVICE USING BLOCK FAMILY ERROR AVOIDANCE
    6.
    发明公开
    DIE FAMILY MANAGEMENT ON A MEMORY DEVICE USING BLOCK FAMILY ERROR AVOIDANCE 审中-公开

    公开(公告)号：US20230393745A1

    公开(公告)日：2023-12-07

    申请号：US17856771

    申请日：2022-07-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Steven Michael Kientz

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/0653

    Abstract: A target block family of a plurality of block families is identified periodically every predetermined number of program erase cycles (PECs) of a memory device. Each block family includes a plurality of blocks. A respective temporal voltage shift of each block of a subset of blocks of the target block family from each die of a plurality of dies associated with the target block family is obtained. A respective die measurement for each respective die is obtained based on an average of the respective temporal voltage shifts of the subset of blocks from each die. Each respective die to a respective die family of a plurality of consecutive die families is assigned based on the respective die measurement for each respective die.

    Tracking and refreshing state metrics in memory sub-systems
    10.
    发明授权
    Tracking and refreshing state metrics in memory sub-systems 有权

    公开(公告)号：US11636913B2

    公开(公告)日：2023-04-25

    申请号：US17301350

    申请日：2021-03-31

    Applicant: Micron Technology, Inc.

    Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steven Michael Kientz

    IPC: G11C16/10 ,  G11C29/42 ,  G11C29/44 ,  G11C16/16 ,  G11C16/26 ,  G11C29/12

    Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. The operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. The operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.

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