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公开(公告)号：US20250117289A1
公开(公告)日：2025-04-10
申请号：US18788550
申请日：2024-07-30
Applicant: Micron Technology, Inc.
Inventor： Charles S. Kwong , Seungjune Jeon , Jun Wan
Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to detect read errors in one or more memory cells using a plurality of read thresholds. The controller selects, for inspection, a target valley of a plurality of valleys associated with an individual memory component of the set of memory components. The controller reads the target valley using a first read threshold to obtain a first set of data and reads the target valley using a second read threshold to obtain a second set of data. The controller compares the first set of data to the second set of data and performs one or more memory operations on the target valley in response to comparing the first set of data to the second set of data.
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公开(公告)号：US20240385926A1
公开(公告)日：2024-11-21
申请号：US18661526
申请日：2024-05-10
Applicant: Micron Technology, Inc.
Inventor： Steven Michael Kientz , Hyungseok Kim , Zixiang Loh , Patrick R. Khayat , Jun Wan
Abstract: A system having a processing device operatively coupled with a memory device to perform the following operations: responsive to detecting a triggering event, measuring a temperature of the memory device to obtain a suspend temperature value, enabling a suspend temperature flag to indicate that temperature input for a step of an error handling operation is based on the suspend temperature value. Updating an operating temperature with the suspend temperature value. Determining, using a data structure which maps temperatures to read level offsets, a read level offset for the step of the error handling operation, based on the operating temperature. Causing the step of the error handling operation to be performed on a set of cells using a read level value based on the read level offset and a base read level, an disabling the suspend temperature flag.
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公开(公告)号：US20250014654A1
公开(公告)日：2025-01-09
申请号：US18758496
申请日：2024-06-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Patrick R. Khayat , Hyungseok Kim , Steven Michael Kientz , Zixiang Loh , Jun Wan
Abstract: A system includes a memory device; and a processing device, operatively coupled to the memory device, the processing device to perform operations including: receiving a request to perform a read operation, the request identifying a set of memory cells in a portion of a memory device; determining a first temperature of the set of memory cells, wherein the first temperature is associated with a first error handing operation of an error handling flow directed to the set of memory cells; determining an offset value to be applied to a temperature compensation coefficient of a parameter of a set of parameters associated with the set of memory cells, wherein the offset value is associated with a temperature range comprising the first temperature; determining a second temperature of the set of memory cells, wherein the second temperature is associated with a second error handling operation following the first error handing operation of the error handling flow directed to the set of memory cells; and responsive to determining that the second temperature falls in the temperature range comprising the first temperature, adjusting, based on the offset value, a temperature compensation value used in the second error handling operation.
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公开(公告)号：US20250004647A1
公开(公告)日：2025-01-02
申请号：US18677578
申请日：2024-05-29
Applicant: Micron Technology, Inc.
Inventor： Ying Yu Tai , Jun Wan , Seungjune Jeon , Zhenming Zhou , Jiangli Zhu
IPC: G06F3/06
Abstract: A processing device analyzes one or more property and capability characteristics of a plurality of memory devices produced in a development process executed by a memory device development system and identifies respective subsets of the plurality of memory devices having property and capability characteristics that meet respective standards associated with a plurality of different use cases. The processing device further allocates the respective subsets to groups of memory devices corresponding to the different use cases.
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公开(公告)号：US20240177781A1
公开(公告)日：2024-05-30
申请号：US18388506
申请日：2023-11-09
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Jun Wan , Zhenming Zhou
Abstract: A method for partial block read compensation can include receiving a read request that specifies a memory cell connected to a string of series-connected memory cells in an array of memory cells on a memory device, the string located at an intersection of a wordline and a bitline, and causing a first voltage applied to the wordline to which the specified memory cell is connected to ramp to a first predetermined value. The method can include causing a second voltage applied to the bitline to which the specified memory cell is connected to ramp to a second predetermined value, and can include comparing, using a current comparator, a current along the string with a reference current to generate an analog output signal. It can also include causing a voltage offset, based on the analog output signal, to be applied to a read voltage level during a sensing operation.
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Patent Agency Ranking
公开(公告)号：US20250130731A1
公开(公告)日：2025-04-24
申请号：US18786100
申请日：2024-07-26
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Jun Wan , Zhenming Zhou , Ying Tai
IPC: G06F3/06
Abstract: Programming data in memory is described herein. An example apparatus includes an array of memory cells having a plurality of access lines to which the cells are coupled, and a processing device that performs a program operation on the array, including programming data to be stored in one page of cells of the array to the cells of the array coupled to a first one of the access lines, programming additional data to be stored in that page to the cells of the array coupled to a second one of the access lines adjacent to the first one of the access lines, sensing the data programmed to the cells of the array coupled to the first one of the access lines, and programming data to be stored in two pages of cells of the array to the cells of the array coupled to the first one of the access lines.
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公开(公告)号：US20240420784A1
公开(公告)日：2024-12-19
申请号：US18739769
申请日：2024-06-11
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Peng Zhang , Lei Lin , Zhenming Zhou , Jun Wan
Abstract: Aspects of the present disclosure configure a memory sub-system controller to selectively adjust a program pulse for different word line groups of a memory sub-system. The controller receives a request to program data to an individual memory component of a set of memory components. The controller determines that a program erase count (PEC) associated with the individual memory component transgresses a threshold value. The controller, in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusts a predetermined program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG). The controller programs the data to the individual memory component according to the selectively adjusted predetermined Vpgm.
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公开(公告)号：US20250037774A1
公开(公告)日：2025-01-30
申请号：US18917774
申请日：2024-10-16
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Jun Wan , Zhenming Zhou
Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components includes a processing device that initiates a corrective read (CR) operation on a set of memory components. The set of memory components includes a pillar that includes a channel and a plurality of transistors. The processing device applies a charge to a first word line (WL) comprising a first transistor of a plurality of transistors to neutralize charges in the channel and senses a charge distribution of a second WL comprising a second transistor of the plurality of transistors adjacent to the first transistor based on the charge applied to the first WL that neutralized the charges in the channel.
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公开(公告)号：US20240185931A1
公开(公告)日：2024-06-06
申请号：US18521957
申请日：2023-11-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu-Chung Lien , Jun Wan , Zhenming Zhou
CPC classification number: G11C16/3404 , G11C16/10 , G11C16/3459
Abstract: A request to perform a program operation to program a set of memory cells on a memory device is received. A defect indicator associated with the set of memory cells is determined to satisfy a defect condition. A value of a program verify parameter is determined based on the defect indicator. The program operation is performed using the value of the program verify parameter during a program verify phase of the program operation.
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公开(公告)号：US20250104796A1
公开(公告)日：2025-03-27
申请号：US18786016
申请日：2024-07-26
Applicant: Micron Technology, Inc.
Inventor： Jun Wan , Yu-Chung Lien , Zhenming Zhou
Abstract: Devices, methods, and systems for performing corrective sense operations in memory are described herein. An example apparatus includes a memory component including a plurality of groups of memory cells, and a processing device coupled to the memory component and configured to perform a sense operation on the plurality of groups of memory cells, perform a corrective sense operation on a first one of the plurality of groups of memory cells using a corrective value, and perform the corrective sense operation on a second one of the plurality of groups of memory cells using the corrective value.
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