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    Power clamp circuit, chip and dual-clamp method
    1.
    发明授权
    Power clamp circuit, chip and dual-clamp method 有权

    公开(公告)号：US11626726B2

    公开(公告)日：2023-04-11

    申请号：US17458608

    申请日：2021-08-27

    Applicant: MONTAGE TECHNOLOGY CO., LTD.

    Inventor： Chunlai Sun

    IPC: H02H9/04 ,  H01L27/02

    Abstract: The present disclosure provides a power clamp circuit, a chip, and a dual-clamp method. The power clamp circuit is applied to a circuit system to monitor the power supply voltage of the circuit system and includes: an EOS protection module, for outputting an EOS protection triggering signal when it is determined that the circuit system is electrically overstressed based on the power supply voltage; an ESD protection module, for outputting an ESD protection triggering signal when it is determined that an electrostatic event is present in the circuit system based on the power supply voltage; a switch control module, for turning on a discharge path based on the EOS protection signal to discharge an EOS current, and turning on the discharge path based on the ESD protection signal to discharge an electrostatic current.

    SST driving circuit, chip and driving output method
    2.
    发明授权
    SST driving circuit, chip and driving output method 有权

    公开(公告)号：US11626725B2

    公开(公告)日：2023-04-11

    申请号：US17458498

    申请日：2021-08-26

    Applicant: MONTAGE TECHNOLOGY CO., LTD.

    Inventor： Chunlai Sun ,  Juan Du

    IPC: H02H9/04 ,  H03K19/0944 ,  H03K19/00 ,  H03K19/003

    Abstract: The present disclosure provides an SST driving circuit, a chip, and a driving output method. The SST driving circuit includes: a signal driver for driving and outputting a signal to be driven, the signal driver including termination resistors; a first electrostatic current discharge module, providing first discharge paths for electrostatic currents generated in the signal driver; a second electrostatic current discharge module, connected in series with the termination resistors, providing second discharge paths for the electrostatic currents; and a power clamp, used for conducting the power clamp circuit, the first discharge paths and the second discharge paths when a power supply voltage of the signal driver exceeds a clamping voltage. The present disclosure provides different discharge paths, which effectively reduces voltage borne by a protected device through a voltage division method, and improves the device's ability to protect against electrostatic discharge.

    Laminate structure and test method for detecting inter-metal dielectric layer defects
    3.
    发明授权
    Laminate structure and test method for detecting inter-metal dielectric layer defects 有权

    公开(公告)号：US11270918B2

    公开(公告)日：2022-03-08

    申请号：US16423040

    申请日：2019-05-27

    Applicant: MONTAGE TECHNOLOGY CO., LTD.

    Inventor： Xiong Zhang ,  Chunlai Sun ,  Peichun Wang ,  Gang Shi

    IPC: H01L21/66 ,  H01L23/544

    Abstract: The present application disclosed a conducting layer-dielectric layer-conducting layer (CDC) laminate structure and test method for detecting defects of an inter-metal dielectric layer. The laminate structure comprises: a dielectric layer formed on a substrate; a first conducting layer formed at a first side of the dielectric layer, wherein the first conducting layer includes a first metal region and at least one first opening in the first metal region; and a second conducting layer formed at a second side of the dielectric layer opposite to the first conducting layer such that the second conducting layer is separated from the first conducting layer by the dielectric layer, wherein the second conducting layer includes a second metal region and a plurality of second openings in the second metal region. The at least one first opening and the plurality of second openings are configured that a projection of the second metal region on the first conducting layer at least partially overlaps with the first metal region.

    Electrostatic discharge and electrical overstress detection circuit
    4.
    发明授权
    Electrostatic discharge and electrical overstress detection circuit 有权

    公开(公告)号：US12184061B2

    公开(公告)日：2024-12-31

    申请号：US18071712

    申请日：2022-11-30

    Applicant: MONTAGE TECHNOLOGY CO., LTD.

    Inventor： Xiong Zhang ,  Chunlai Sun

    IPC: H02H9/04 ,  G01R31/00

    Abstract: An electrostatic discharge and electrical overstress detection circuit includes protection circuit, sensing circuit, clamp circuit, several stages of sampling logic circuits connected in sequence and storage circuit. Protection circuit is coupled between input/output pin and internal chip and discharges to a power supply terminal when the electrostatic discharge or electrical overstress events happen. Sensing circuit and clamp circuit are coupled between power supply terminal and ground terminal. Each stage of sampling logic circuit is coupled to power supply terminal and memory cell of storage circuit, and the first stage of sampling logic is coupled to the clamp circuit, and when the electrostatic discharge or electrical overstress events happen, the several stages of sampling logic circuits sample voltage of the power supply terminal one by one and change state of corresponding memory cell, so that the electrostatic discharge or electrical overstress events are successively recorded by the memory cell.

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