ASYMMETRICAL I/O STRUCTURE
    1.
    发明申请

    公开(公告)号:US20220060187A1

    公开(公告)日:2022-02-24

    申请号:US17406370

    申请日:2021-08-19

    Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.

    PACKAGE SUBSTRATE STRUCTURE AND METHOD FOR MANUFACTURING SAME

    公开(公告)号:US20220301888A1

    公开(公告)日:2022-09-22

    申请号:US17458238

    申请日:2021-08-26

    Abstract: The present disclosure provides a package substrate structure and a method for manufacturing the same. The method includes: providing a substrate, forming a first hole with a first radial dimension in the substrate; forming a first metal layer on the sidewall of the first via to form a first via; filing the first via with a dielectric layer; forming a second hole with a second radial dimension in the dielectric layer, wherein the second radial dimension is smaller than the first radial dimension, and the second hole and the first metal layer are separated by the dielectric layer; filling the second hole with the second metal layer to form a second via. The high-speed circuit via design achieved by a sleeve via arrangement of the present disclosure can reduce the influence of the impedance mismatch caused by vias on insertion loss and the return loss in a specific frequency band.

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