公开(公告)号：US20220376495A1

公开(公告)日：2022-11-24

申请号：US17458498

申请日：2021-08-26

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Chunlai SUN ,  Juan DU

IPC: H02H9/04 ,  H03K19/003 ,  H03K19/00 ,  H03K19/0944

Abstract: The present disclosure provides an SST driving circuit, a chip, and a driving output method. The SST driving circuit includes: a signal driver for driving and outputting a signal to be driven, the signal driver including termination resistors; a first electrostatic current discharge module, providing first discharge paths for electrostatic currents generated in the signal driver; a second electrostatic current discharge module, connected in series with the termination resistors, providing second discharge paths for the electrostatic currents; and a power clamp, used for conducting the power clamp circuit, the first discharge paths and the second discharge paths when a power supply voltage of the signal driver exceeds a clamping voltage. The present disclosure provides different discharge paths, which effectively reduces voltage borne by a protected device through a voltage division method, and improves the device's ability to protect against electrostatic discharge.

公开(公告)号：US20220060187A1

公开(公告)日：2022-02-24

申请号：US17406370

申请日：2021-08-19

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Xiong ZHANG ,  Chunlai SUN ,  Juan DU ,  Gang SHI ,  Chonghe YANG

IPC: H03K19/0944 ,  H03K19/003 ,  H03K19/00 ,  H03K17/687 ,  H03K17/10

Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.