公开(公告)号：US20120236643A1

公开(公告)日：2012-09-20

申请号：US13289966

申请日：2011-11-04

Applicant: Mark MOSHAYEDI

Inventor： Mark MOSHAYEDI

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G06F12/0246 ,  G06F12/0607 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C16/102 ,  G11C16/26

Abstract: A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally, the flash storage system may asynchronously read data portions of a data block interleaved among the storage blocks, store the data portions in the data buffer, and access the data portions from the data buffer.

Abstract translation: 闪存存储系统访问在闪存存储设备之间交错的数据。 闪存存储系统接收包括数据部分的数据块，将数据部分存储在数据缓冲器中，并且启动数据传输以异步地将数据部分写入闪存存储器件之间交错的存储块中。 此外，闪速存储系统可以异步地读取在存储块之间交错的数据块的数据部分，将数据部分存储在数据缓冲器中，并从数据缓冲器访问数据部分。

公开(公告)号：US20100327436A1

公开(公告)日：2010-12-30

申请号：US12828175

申请日：2010-06-30

Applicant: Mark MOSHAYEDI

Inventor： Mark MOSHAYEDI

IPC: H01L23/498 ,  H01L23/52

CPC classification number: H05K1/181 ,  H01L23/50 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09072 ,  H05K2201/0949 ,  H05K2201/10515 ,  H05K2201/10666 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.

Abstract translation: 多芯片堆叠模块为给定的表面芯片占用空间提供了增加的电路密度。 支撑结构与标准表面贴装型芯片交替形成堆叠，其中支撑结构将芯片电互连。 一个方面是用于在垂直堆叠中互连多个大致平面的芯片的结构和方法，使得在堆叠中共同连接的芯片的信号和单独访问的信号在堆栈内分离。

公开(公告)号：US20100205470A1

公开(公告)日：2010-08-12

申请号：US12369052

申请日：2009-02-11

Applicant: Mark MOSHAYEDI ,  Douglas Finke

Inventor： Mark MOSHAYEDI ,  Douglas Finke

IPC: G06F1/28 ,  G06F13/42

CPC classification number: G11C5/141 ,  G11C5/143 ,  G11C7/24 ,  G11C2029/4402

Abstract: A memory device includes: volatile memory; an interface for connecting to a backup power source; non-volatile memory; a first configuration data bus for accessing parameters describing substantially permanent characteristics of the volatile memory; a second configuration data bus for accessing at least one of state of health information of the backup power source and status information of the memory device, wherein the first configuration data bus and the second configuration data bus implement a same bus protocol; a controller programmed to detect a loss of power of a primary power source and move data from the volatile memory to the non-volatile memory, wherein configuration information of the controller is at least one of readable and writable through the first configuration data bus; and wherein at least one of the state-of-health information and the status information is at least one of readable and writable through the second configuration data bus.

Abstract translation: 存储器件包括：易失性存储器; 用于连接到备用电源的接口; 非易失性存储器 第一配置数据总线，用于访问描述所述易失性存储器的基本上永久特性的参数; 第二配置数据总线，用于访问备用电源的健康状态信息和存储器件的状态信息中的至少一个，其中第一配置数据总线和第二配置数据总线实现相同的总线协议; 控制器被编程为检测主电源的功率损失并将数据从易失性存储器移动到非易失性存储器，其中控制器的配置信息是通过第一配置数据总线可读和写的至少一个; 并且其中所述健康状态信息和所述状态信息中的至少一个是通过所述第二配置数据总线可读和写入中的至少一个。

公开(公告)号：US20080228895A1

公开(公告)日：2008-09-18

申请号：US12129634

申请日：2008-05-29

Applicant: Mark MOSHAYEDI

Inventor： Mark MOSHAYEDI

IPC: G06F15/16

CPC classification number: H04L67/06

Abstract: A computing host includes a communication processor that receives a file request from a computer network for transferring a file between the computer network and a storage device. If the file is directly transferable between the computer network and the storage device without a need for processing the file by a host processor of the computing host, the communication processor performs the file transfer. Otherwise, the host processor processes the file and performs the file transfer.

Abstract translation: 计算主机包括从计算机网络接收文件请求以在计算机网络和存储设备之间传送文件的通信处理器。 如果文件可以在计算机网络和存储设备之间直接传输，而不需要由计算主机的主机处理器处理文件，则通信处理器执行文件传送。 否则，主机处理器处理文件并执行文件传输。

公开(公告)号：US20120324299A1

公开(公告)日：2012-12-20

申请号：US13597158

申请日：2012-08-28

Applicant: Mark MOSHAYEDI

Inventor： Mark MOSHAYEDI

IPC: G06F11/08

CPC classification number: G11C29/76 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7211

Abstract: A flash storage device performs wear-leveling by tracking data errors that occur when dynamic data is read from a storage block of the flash storage device and moving the dynamic data to an available storage block of the flash storage device. Additionally, the flash storage device identifies a storage block containing static data and moves the static data to the storage block previously containing the dynamic data.

Abstract translation: 闪存存储设备通过跟踪当从闪存存储设备的存储块读取动态数据并且将动态数据移动到闪存存储设备的可用存储块时发生的数据错误来执行磨损均衡。 此外，闪存存储设备识别包含静态数据的存储块，并将静态数据移动到先前包含动态数据的存储块。

公开(公告)号：US20110022783A1

公开(公告)日：2011-01-27

申请号：US12509405

申请日：2009-07-24

Applicant: Mark MOSHAYEDI

Inventor： Mark MOSHAYEDI

IPC: G06F12/00 ,  G06F13/14 ,  G06F12/02

CPC classification number: G06F13/385 ,  G06F2212/7208 ,  G06F2213/3854

Abstract: A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules.

Abstract translation: 闪存存储系统包括通过通用串行总线耦合到闪存阵列的存储模块的闪存控制器。 每个存储模块包括至少一个闪存器件。 闪存控制器接收通信协议的编程命令，并根据编程命令生成通用串行总线命令。 闪存控制器通过通用串行总线向闪存阵列中的存储模块发出通用串行总线命令。 存储模块处理通用串行总线命令以访问存储模块的闪存存储设备中的数据。

公开(公告)号：US20100205348A1

公开(公告)日：2010-08-12

申请号：US12369046

申请日：2009-02-11

Applicant: Mark MOSHAYEDI ,  Douglas Finke

Inventor： Mark MOSHAYEDI ,  Douglas Finke

IPC: G06F13/00

CPC classification number: G11C14/0018 ,  G06F1/30 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/0727 ,  G06F11/1402 ,  G11C5/14 ,  G11C5/141 ,  G11C5/143

Abstract: A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and parameters describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the parameters include serial presence detect information.

Abstract translation: 一个设备包括易失性存储器; 一个或多个非易失性存储器芯片，每个非易失性存储器芯片用于存储从易失性存储器移动的数据; 用于连接到备用电源的接口，其布置成在来自主电源的电力丢失时临时对所述易失性存储器供电; 与易失性存储器和非易失性存储器通信的控制器，其中：控制器被编程为在易失性存储器的主电源的功率损失时将数据从易失性存储器移动到非易失性存储器芯片; 并且描述易失性存储器的参数存储在存储从易失性存储器移动的数据的至少一个非易失性存储器芯片中。 在某些方面，参数包括串行存在检测信息。

公开(公告)号：US20120317406A1

公开(公告)日：2012-12-13

申请号：US13590123

申请日：2012-08-20

Applicant: Mark MOSHAYEDI

Inventor： Mark MOSHAYEDI

IPC: G06F9/24 ,  G06F12/00

CPC classification number: G06F9/4401

Abstract: The subject technology relates to a flash storage system for accessing a boot program for a computing system, the flash storage system comprising a flash storage, a random access memory and a flash controller coupled to the flash storage and the random access memory, the flash controller configured to load the boot program from the flash storage into the random access memory. In certain aspects, the flash control is further configured to generate a ready signal indicating the boot program is accessible from the random access memory. Computing systems and methods are also provided.

Abstract translation: 主题技术涉及一种用于访问用于计算系统的引导程序的闪存系统，闪存存储系统包括闪存存储器，随机存取存储器和耦合到闪速存储器和随机存取存储器的闪存控制器，闪存控制器 配置为将引导程序从闪存存储器加载到随机存取存储器中。 在某些方面，闪存控制还被配置为产生指示可以从随机存取存储器访问引导程序的就绪信号。 还提供了计算系统和方法。

公开(公告)号：US20100202239A1

公开(公告)日：2010-08-12

申请号：US12369027

申请日：2009-02-11

Applicant: Mark MOSHAYEDI ,  Douglas FINKE

Inventor： Mark MOSHAYEDI ,  Douglas FINKE

IPC: G11C5/14

CPC classification number: G11C16/30 ,  G11C5/04 ,  G11C5/141 ,  G11C5/143 ,  G11C5/147

Abstract: A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory at least one memory portion at a time, and while moving data from the volatile memory to the non-volatile memory place the memory portions from which data is being moved into a normal operating state and the memory portions from which data is not being moved into a low-power state.

Abstract translation: 一种与主电源一起使用的存储器件包括：易失性存储器，包括多个存储器部分，每个存储器部分具有正常工作状态和低功率状态; 用于连接到备用电源的接口，所述备用电源被布置成在来自所述主电源的电力丢失时临时对所述易失性存储器供电; 非易失性存储器; 以及控制器，其与所述易失性存储器和所述非易失性存储器通信，所述控制器被编程为检测所述主电源的功率损失，并且响应于将数据从所述易失性存储器移动到所述非易失性存储器，至少一个存储器部分 并且当将数据从易失性存储器移动到非易失性存储器时，将数据移动到正常操作状态的存储器部分和数据未被移动到低功率状态的存储器部分。

公开(公告)号：US20090327804A1

公开(公告)日：2009-12-31

申请号：US12464856

申请日：2009-05-12

Applicant: Mark MOSHAYEDI

Inventor： Mark MOSHAYEDI

IPC: G06F11/20 ,  G06F12/00 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1441

Abstract: A method of wear leveling in a flash storage device comprising a plurality of data blocks is provided. The method comprises the steps of detecting a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks, correcting the data error, and moving the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks.

Abstract translation: 提供了一种包括多个数据块的闪存存储设备中的磨损均衡方法。 该方法包括以下步骤：检测来自多个数据块中的第一数据块的第一数据段的动态数据的读取中的数据错误，校正数据错误，以及将动态数据从第一数据段移动到 第二数据段在多个数据块中的第二数据块中。