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Patent Agency Ranking
公开(公告)号：US10187017B2
公开(公告)日：2019-01-22
申请号：US15478713
申请日：2017-04-04
Applicant: MaxLinear, Inc.
Inventor： Prasun Kali Bhattacharyya , Abhishek Ghosh , Prasenjit Bhowmik
Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.
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公开(公告)号：US20160344398A1
公开(公告)日：2016-11-24
申请号：US15160496
申请日：2016-05-20
Applicant: MaxLinear, Inc.
Inventor： Prasun Kali Bhattacharyya , Prasenjit Bhowmik , Vamsi Paidi
CPC classification number: H03L7/235
Abstract: Systems and methods are provided for cascaded phase-locked loops (PLLs). A plurality of phase-locked loops (PLLs) arranged in a cascaded manner may be used in providing enhanced signal generation. Each PLL generates an output based on a corresponding input and a feedback signal. The input to a first one of plurality of cascaded phase-locked loops (PLLs) comprises an input reference signal; the input to each remaining one of the plurality of the cascaded phase-locked loops (PLLs) corresponds to an output of a preceding one of the plurality of the cascaded phase-locked loops (PLLs); and the output of a last one of the plurality of cascaded phase-locked loops (PLLs) corresponds to an overall output signal of the plurality of cascaded phase-locked loops (PLLs). The frequency of the overall output signal is set based on the one or more adjustments applied in each one of the plurality of cascaded phase-locked loops (PLLs).
Abstract translation: 为级联锁相环（PLL）提供系统和方法。 以级联方式布置的多个锁相环（PLL）可用于提供增强的信号产生。 每个PLL根据相应的输入和反馈信号产生输出。 多个级联锁相环（PLL）中的第一个的输入包括输入参考信号; 对多个级联锁相环（PLL）中的每个剩余的一个的输入对应于多个级联锁相环（PLL）中的前一个的输出; 并且多个级联锁相环（PLL）中的最后一个的输出对应于多个级联锁相环（PLL）的总输出信号。 基于在多个级联锁相环（PLL）中的每一个中施加的一个或多个调整来设置总输出信号的频率。
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公开(公告)号：US20180198419A1
公开(公告)日：2018-07-12
申请号：US15478713
申请日：2017-04-04
Applicant: MaxLinear, Inc.
Inventor： Prasun Kali Bhattacharyya , Abhishek Ghosh , Prasenjit Bhowmik
CPC classification number: H03F1/32 , G11B20/22 , H03F3/19 , H03F3/24 , H03F2200/451 , H03M1/0614 , H03M1/0624 , H03M1/66 , H04B1/0475 , H04B1/10 , H04L7/0008
Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.
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公开(公告)号：US20200021250A1
公开(公告)日：2020-01-16
申请号：US16584423
申请日：2019-09-26
Applicant: MaxLinear, Inc.
Inventor： Prasun Kali Bhattacharyya , Abhishek Ghosh , Prasenjit Bhowmik
Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may include at least two processing paths, each including at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may include adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.
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公开(公告)号：US20190341892A1
公开(公告)日：2019-11-07
申请号：US16400483
申请日：2019-05-01
Applicant: Maxlinear, Inc.
Inventor： Anand Mohan Pappu , Ranjit Kumar Guntreddi , Madhusudan Govindarajan , Pranjal Pandey , Prasenjit Bhowmik
Abstract: A transconductance circuit comprises a first transistor, a second transistor, a first source-degeneration device, a second source-degeneration device, a first feedback device, and a second feedback device. The gate node of the first transistor is coupled to a source node of the second transistor via the first feedback device. The gate node of the second transistor is coupled to a source node of the second transistor via the second feedback device. The source node of the first transistor is coupled to a reference voltage via the first source-degeneration device. The source node of the second transistor is coupled to the reference voltage via the second source-degeneration device.
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