公开(公告)号：US11923272B2

公开(公告)日：2024-03-05

申请号：US17721919

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Zhuo Chen ,  Irina V. Vasilyeva ,  Darwin Franseda Fan ,  Kamal Kumar Muthukrishnan

IPC: H01L21/48 ,  H01L23/48 ,  H10B12/00 ,  H10B53/10 ,  H10B53/30 ,  H10B53/40

CPC classification number: H01L23/481 ,  H01L21/4814 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/50 ,  H10B53/10 ,  H10B53/30 ,  H10B53/40

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

公开(公告)号：US20210005619A1

公开(公告)日：2021-01-07

申请号：US16503178

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Kamal Kumar Muthukrishnan ,  Alex J. Schrinsky

IPC: H01L27/11502 ,  G11C11/22 ,  H01L29/51 ,  H01L27/108

Abstract: Integrated circuitry comprises a plurality of features horizontally arrayed in a two-dimensional (2D) lattice. The 2D lattice comprises a parallelogram unit cell having four lattice points and four straight-line sides between pairs of the four lattice points. The parallelogram unit cell has a straight-line diagonal there-across between two diagonally-opposed of the four lattice points. The straight-line diagonal is longer than each of the four straight-line sides. Individual of the features are at one of the four lattice points and occupy a maximum horizontal area that is horizontally elongated along a direction that is horizontally angled relative to each of the four straight-line sides. Other embodiments, including methods, are disclosed

公开(公告)号：US11935574B2

公开(公告)日：2024-03-19

申请号：US17496564

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Ashonita A. Chavan ,  Sameer Chhajed ,  Beth R. Cook ,  Kamal Kumar Muthukrishnan ,  Durai Vishak Nirmal Ramaswamy ,  Lance Williamson

IPC: H01L21/00 ,  G11C11/22 ,  H01L49/02 ,  H10B53/00

CPC classification number: G11C11/221 ,  H01L28/60 ,  H10B53/00

Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

公开(公告)号：US11170834B2

公开(公告)日：2021-11-09

申请号：US16507826

申请日：2019-07-10

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Ashonita A. Chavan ,  Sameer Chhajed ,  Beth R. Cook ,  Kamal Kumar Muthukrishnan ,  Durai Vishak Nirmal Ramaswamy ,  Lance Williamson

IPC: G11C11/22 ,  H01L49/02 ,  H01L27/11502

Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

公开(公告)号：US20210012824A1

公开(公告)日：2021-01-14

申请号：US16507826

申请日：2019-07-10

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Ashonita A. Chavan ,  Sameer Chhajed ,  Beth R. Cook ,  Kamal Kumar Muthukrishnan ,  Durai Vishak Nirmal Ramaswamy ,  Lance Williamson

IPC: G11C11/22 ,  H01L27/11502 ,  H01L49/02

Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

公开(公告)号：US20220238417A1

公开(公告)日：2022-07-28

申请号：US17721919

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Zhuo Chen ,  Irina V. Vasilyeva ,  Darwin Franseda Fan ,  Kamal Kumar Muthukrishnan

IPC: H01L23/48 ,  H01L27/108 ,  H01L27/11504 ,  H01L21/48 ,  H01L27/11507 ,  H01L27/11509

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

公开(公告)号：US11335626B2

公开(公告)日：2022-05-17

申请号：US17021793

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Zhuo Chen ,  Irina V. Vasilyeva ,  Darwin Franseda Fan ,  Kamal Kumar Muthukrishnan

IPC: H01L23/48 ,  H01L27/108 ,  H01L27/11504 ,  H01L21/48 ,  H01L27/11507 ,  H01L27/11509

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

公开(公告)号：US20220084906A1

公开(公告)日：2022-03-17

申请号：US17021793

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Zhuo Chen ,  Irina V. Vasilyeva ,  Darwin Franseda Fan ,  Kamal Kumar Muthukrishnan

IPC: H01L23/48 ,  H01L27/108 ,  H01L27/11504 ,  H01L27/11509 ,  H01L27/11507 ,  H01L21/48

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

公开(公告)号：US20220028442A1

公开(公告)日：2022-01-27

申请号：US17496564

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Ashonita A. Chavan ,  Sameer Chhajed ,  Beth R. Cook ,  Kamal Kumar Muthukrishnan ,  Durai Vishak Nirmal Ramaswamy ,  Lance Williamson

IPC: G11C11/22 ,  H01L49/02 ,  H01L27/11502

Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

公开(公告)号：US11139309B2

公开(公告)日：2021-10-05

申请号：US16503178

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Kamal Kumar Muthukrishnan ,  Alex J. Schrinsky

IPC: H01L27/11502 ,  G11C11/22 ,  H01L27/108 ,  H01L29/51

Abstract: Integrated circuitry comprises a plurality of features horizontally arrayed in a two-dimensional (2D) lattice. The 2D lattice comprises a parallelogram unit cell having four lattice points and four straight-line sides between pairs of the four lattice points. The parallelogram unit cell has a straight-line diagonal there-across between two diagonally-opposed of the four lattice points. The straight-line diagonal is longer than each of the four straight-line sides. Individual of the features are at one of the four lattice points and occupy a maximum horizontal area that is horizontally elongated along a direction that is horizontally angled relative to each of the four straight-line sides. Other embodiments, including methods, are disclosed.