SELF-ALIGNED TECHNIQUES FOR FORMING CONNECTIONS IN A MEMORY DEVICE

    公开(公告)号:US20240045604A1

    公开(公告)日:2024-02-08

    申请号:US17879581

    申请日:2022-08-02

    CPC classification number: G06F3/0635 G06F3/0604 G06F3/0679

    Abstract: Methods, systems, and devices for self-aligned techniques for forming connections in a memory device are described. A redistribution layer (RDL) for coupling an electrode of a capacitor of a memory cell with a corresponding selector device may be fabricated at a same time or stage as the electrode, using self-aligned techniques. When forming portions of a memory cell, a cavity for the electrode may be etched, and a portion of the RDL that extends from the electrode cavity to a corresponding selector device may also be selectively etched. The resulting cavities may be filled with an electrode material, which may form the electrode and couple the electrode to the corresponding selector device. The resulting memory device may support implementation of a staggered configuration for memory cells, and may include electrodes that share a crystalline structure with one or more corresponding portions of an RDL.

    ELECTRONIC DEVICES INCLUDING CAPACITORS, AND RELATED METHODS

    公开(公告)号:US20250063737A1

    公开(公告)日:2025-02-20

    申请号:US18753940

    申请日:2024-06-25

    Abstract: An electronic device comprises a memory array comprising access lines, data lines, and memory cells. Each memory cell is coupled to an associated access line and an associated data line and each memory cell comprises an access device, and a capacitor adjacent to the access device. The capacitor comprises a first electrode, a second electrode separated from the first electrode by an insulative material, and a leaker device adjacent to the first electrode. The second electrode and the leaker device extend through a lattice insulative material adjacent to the first electrode. The leaker device exhibits a substantially circular cross-sectional shape in a direction that is transverse to a direction in which the leaker device extends, with portions of the leaker device extending within a recessed region of the insulative material. Methods of forming electronic devices are also disclosed.

    Integrated Assemblies and Methods of Forming Integrated Assemblies

    公开(公告)号:US20220238417A1

    公开(公告)日:2022-07-28

    申请号:US17721919

    申请日:2022-04-15

    Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

    Integrated assemblies and methods of forming integrated assemblies

    公开(公告)号:US11335626B2

    公开(公告)日:2022-05-17

    申请号:US17021793

    申请日:2020-09-15

    Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

    Integrated Assemblies and Methods of Forming Integrated Assemblies

    公开(公告)号:US20220084906A1

    公开(公告)日:2022-03-17

    申请号:US17021793

    申请日:2020-09-15

    Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

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