公开(公告)号：US20230187143A1

公开(公告)日：2023-06-15

申请号：US18065188

申请日：2022-12-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Brigitte SOULIER ,  Frédéric VOIRON ,  Jullen EL SABAHY

IPC: H01G4/33 ,  H01G4/012 ,  C25D11/18 ,  C25D11/02

CPC classification number: H01G4/33 ,  H01L28/82 ,  H01G4/012 ,  C25D11/18 ,  C25D11/022

Abstract: A method for manufacturing an electrical device that includes: anodizing a portion of an anodizable metal layer so as to obtain an anodic porous oxide region and an anodizable metal region adjoining the anodic porous oxide region, the anodic porous oxide region being thicker than the anodizable metal region; depositing a layer of liner material on the anodic porous oxide region and on the anodizable metal region; depositing a layer of filler material on the layer of liner material to obtain a stacked structure having a top surface; planarizing the stacked structure from a top surface thereof until reaching the layer of the liner material, so as to expose a portion of liner material located above at least a portion of the anodic porous oxide region; and removing the exposed portion of liner material.

公开(公告)号：US20230197440A1

公开(公告)日：2023-06-22

申请号：US18153585

申请日：2023-01-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Brigitte SOULIER ,  Frédéric VOIRON

IPC: H01L21/02 ,  H01G4/33 ,  C25D11/02 ,  C25D11/32 ,  C25D11/04

CPC classification number: H01L21/02258 ,  C25D11/022 ,  C25D11/32 ,  C25D11/045 ,  H01G4/33 ,  H01L21/02178 ,  H01L21/02244 ,  H01L28/92 ,  H01G4/10

Abstract: An electrical device that includes: a metal barrier layer; an anodic porous oxide region on the metal barrier layer; a trench around the anodic porous oxide region reaching the metal barrier layer; a liner at least on a wall of the trench on a side of the anodic porous oxide region forming an electrical isolation barrier and having an opening onto the anodic porous oxide region; a hard mask arranged above the trenches and the liner having an opening onto the anodic porous oxide region. A corresponding manufacturing method is also disclosed.

公开(公告)号：US20230245834A1

公开(公告)日：2023-08-03

申请号：US18297057

申请日：2023-04-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Larry BUFFLE ,  Frédéric VOIRON ,  Julien EL SABAHY ,  Brigitte SOULIER

IPC: H01G4/33 ,  H01G4/012 ,  H01G4/10

CPC classification number: H01G4/33 ,  H01G4/10 ,  H01G4/012 ,  H01L28/87 ,  H01L28/91 ,  H01G4/085

Abstract: An electrical device that includes: a substrate; an anodic porous oxide region above the substrate; a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the first capacitor electrode region having a first wall perpendicular to the top surface; a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region, the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region.

公开(公告)号：US20240213018A1

公开(公告)日：2024-06-27

申请号：US18394137

申请日：2023-12-22

Applicant: Murata Manufacturing Co., Ltd. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Brigitte SOULIER ,  Sophie Archambault ,  Frédéric Voiron ,  Floriane Baudin ,  Sébastien Dominguez

IPC: H01L21/02

CPC classification number: H01L21/02258 ,  H01L28/60 ,  H01L21/02178

Abstract: A method of manufacturing an integrated device that includes: forming, on a substrate, a metal anodization barrier layer; planarizing the metal anodization barrier layer; forming, on the planarized metal anodization barrier layer, an anodizable metal layer; planarizing the anodizable metal layer; and anodizing the planarized anodizable metal layer to obtain an anodic porous oxide region having a plurality of substantially straight pores that extend from a top surface of the anodic porous oxide region towards the metal anodization barrier layer.

公开(公告)号：US20220352024A1

公开(公告)日：2022-11-03

申请号：US17858116

申请日：2022-07-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Frédéric VOIRON ,  Brigitte SOULIER ,  Hiroshi NAKAGAWA

IPC: H01L21/78 ,  H01L21/3213

Abstract: A method of fabricating a semiconductor structure that includes: forming a first metal layer over a wafer; forming a second metal layer over the first metal layer; forming a first porous structure in a first region of the second metal layer located above a circuit area of the wafer and a second porous structure in a second region of the second metal layer located above a dicing area of the wafer, wherein the first porous structure includes a first set of pores, and wherein the second porous structure includes a second set of pores; forming a metal-insulator-metal stack in the first set of pores of the first porous structure; and etching the second set of pores of the second porous structure to expose the dicing area of the silicon wafer.

公开(公告)号：US20230307185A1

公开(公告)日：2023-09-28

申请号：US18328059

申请日：2023-06-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Frédéric VOIRON ,  Brigitte SOULIER ,  Julien EL SABAHY

IPC: H01G4/228 ,  H01G4/33 ,  H01G4/01

CPC classification number: H01G4/228 ,  H01G4/33 ,  H01G4/01

Abstract: A capacitor structure that includes a substrate; a conductive layer above the substrate; and a porous layer, above the conductive layer, having pores that extend perpendicularly from a top surface of the porous layer toward the conductive layer. The porous layer comprises a first region in which pores conductive wires are disposed, and a second region in which pores a metal-insulator-metal (MIM) structure is disposed. The first region may be used as a via to contact a bottom electrode of the capacitor structure.