公开(公告)号：US20160351678A1

公开(公告)日：2016-12-01

申请号：US15199413

申请日：2016-06-30

Applicant: Nanya Technology Corp.

Inventor： Shin-Yu Nieh ,  Tieh-Chiang Wu ,  Wei-Ming Liao ,  Jei-Cheng Huang ,  Hai-Han Hung ,  Hsiu-Chun Lee

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.

Abstract translation: 本发明提供了一种制造半导体器件的方法，包括：在衬底上形成虚拟栅极，在虚拟栅极和衬底上形成层间电介质层（ILD），在虚设的上表面上形成金属层 栅极，去除伪栅极以在层间电介质层（ILD）中形成沟槽，在沟槽中共形形成栅极电介质层，在栅极电介质层上共形形成第一导电型金属层，各向异性蚀刻第一导电 型金属层和金属层上的栅极电介质层，以在层间电介质层（ILD）中形成间隙，并在间隙中填充第二导电型金属层。

公开(公告)号：US09985105B2

公开(公告)日：2018-05-29

申请号：US15199413

申请日：2016-06-30

Applicant: Nanya Technology Corp.

Inventor： Shin-Yu Nieh ,  Tieh-Chiang Wu ,  Wei-Ming Liao ,  Jei-Cheng Huang ,  Hai-Han Hung ,  Hsiu-Chun Lee

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.

公开(公告)号：US20140264640A1

公开(公告)日：2014-09-18

申请号：US13846169

申请日：2013-03-18

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shin-Yu Nieh ,  Tieh-Chiang Wu ,  Wei-Ming Liao ,  Jei-Cheng Huang ,  Hai-Han Hung ,  Hsiu-Chun Lee

IPC: H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

Abstract: The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer.

Abstract translation: 本发明提供一种半导体器件，包括：衬底; 形成在所述基板上的U形栅介质层; 以及在U形栅极电介质层的内表面上的双功函数金属栅极层，其中双功函数金属栅极层包括第一导电型金属层和第二导电型金属层。