公开(公告)号：US20160351678A1

公开(公告)日：2016-12-01

申请号：US15199413

申请日：2016-06-30

Applicant: Nanya Technology Corp.

Inventor： Shin-Yu Nieh ,  Tieh-Chiang Wu ,  Wei-Ming Liao ,  Jei-Cheng Huang ,  Hai-Han Hung ,  Hsiu-Chun Lee

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.

Abstract translation: 本发明提供了一种制造半导体器件的方法，包括：在衬底上形成虚拟栅极，在虚拟栅极和衬底上形成层间电介质层（ILD），在虚设的上表面上形成金属层 栅极，去除伪栅极以在层间电介质层（ILD）中形成沟槽，在沟槽中共形形成栅极电介质层，在栅极电介质层上共形形成第一导电型金属层，各向异性蚀刻第一导电 型金属层和金属层上的栅极电介质层，以在层间电介质层（ILD）中形成间隙，并在间隙中填充第二导电型金属层。

公开(公告)号：US20150123195A1

公开(公告)日：2015-05-07

申请号：US14070589

申请日：2013-11-04

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tieh-Chiang Wu ,  Wei-Ming Liao

IPC: H01L29/423 ,  H01L29/76 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/265 ,  H01L21/28008 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10855 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/76

Abstract: A recessed channel access transistor device is provided. A semiconductor substrate having thereon a trench is provided. The trench extends from a main surface of the semiconductor substrate to a predetermined depth. A buried gate electrode is disposed at a lower portion of the trench. A gate oxide layer is formed between the buried gate electrode and the semiconductor substrate. A drain doping region on a first side (cell side) of the trench in the semiconductor substrate and a source doping region on a second side (digit side) of the trench are formed. The source doping region has a junction depth that is deeper than that of the drain doping region. An L-shaped channel is defined along a sidewall surface on the first side and along a bottom surface of the trench between the drain doping region and the source doping region.

Abstract translation: 提供凹陷通道存取晶体管器件。 提供其上具有沟槽的半导体衬底。 沟槽从半导体衬底的主表面延伸到预定的深度。 掩埋栅电极设置在沟槽的下部。 在掩埋栅电极和半导体衬底之间形成栅氧化层。 形成半导体衬底中的沟槽的第一侧（单元侧）上的漏极掺杂区域和沟槽的第二侧（数字侧）的源极掺杂区域。 源极掺杂区域具有比漏极掺杂区域深的结深度。 沿沟槽的第一侧的侧壁表面和漏极掺杂区域和源极掺杂区域之间的沟槽的底表面限定L形沟道。

公开(公告)号：US20150155367A1

公开(公告)日：2015-06-04

申请号：US14616750

申请日：2015-02-09

Applicant: Nanya Technology Corp.

Inventor： Tieh-Chiang Wu ,  Wei-Ming Liao

IPC: H01L29/66 ,  H01L21/265 ,  H01L27/108 ,  H01L21/28

CPC classification number: H01L29/66666 ,  H01L21/265 ,  H01L21/28008 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10855 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/76

Abstract: A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region.

Abstract translation: 沟槽从半导体衬底的主表面延伸到预定深度。 在沟槽中形成栅极氧化层。 掩埋栅电极形成在沟槽的下部。 掩埋栅极电极被覆盖有介电层。 衬底层和硬掩模层形成在半导体衬底上。 通过焊盘层和硬掩模层并进入半导体衬底的凹陷形成在沟槽的一侧。 介电层的一部分露出在凹槽内。 然后去除硬掩模层。 执行离子注入工艺以在沟槽的两侧上注入掺杂剂，由此形成源极掺杂区域和漏极掺杂区域。 源极掺杂区域具有比漏极掺杂区域深的结深度。

公开(公告)号：US09343547B2

公开(公告)日：2016-05-17

申请号：US14616750

申请日：2015-02-09

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tieh-Chiang Wu ,  Wei-Ming Liao

IPC: H01L29/66 ,  H01L29/76 ,  H01L21/265 ,  H01L21/28 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/265 ,  H01L21/28008 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10855 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/76

Abstract: A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region.

Abstract translation: 沟槽从半导体衬底的主表面延伸到预定深度。 在沟槽中形成栅极氧化层。 掩埋栅电极形成在沟槽的下部。 掩埋栅极电极被覆盖有介电层。 衬底层和硬掩模层形成在半导体衬底上。 通过焊盘层和硬掩模层并进入半导体衬底的凹陷形成在沟槽的一侧。 介电层的一部分露出在凹槽内。 然后去除硬掩模层。 执行离子注入工艺以在沟槽的两侧上注入掺杂剂，由此形成源极掺杂区域和漏极掺杂区域。 源极掺杂区域具有比漏极掺杂区域深的结深度。

公开(公告)号：US08865550B2

公开(公告)日：2014-10-21

申请号：US14184725

申请日：2014-02-20

Applicant: Nanya Technology Corp.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/66 ,  H01L29/66 ,  H01L27/108 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/66666 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

公开(公告)号：US20140213027A1

公开(公告)日：2014-07-31

申请号：US14184725

申请日：2014-02-20

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

Abstract translation: 提供一种形成掩埋位线的方法。 提供衬底并且在衬底中限定线状沟槽区域。 在基板的线状沟槽区域中形成线状沟槽。 线状沟槽包括侧壁表面和底部表面。 然后，将线状沟槽的底面加宽，形成弯曲的底面。 接下来，在与该弯曲底面相邻的基板上形成掺杂区域。 最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。

公开(公告)号：US20130307067A1

公开(公告)日：2013-11-21

申请号：US13958620

申请日：2013-08-05

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/423

CPC classification number: H01L29/4236 ,  H01L21/28114 ,  H01L21/76224 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66553

Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.

Abstract translation: 提供狭缝凹槽通道门。 狭缝凹槽通道门包括衬底，栅介质层，第一导电层和第二导电层。 衬底具有第一沟槽。 栅介质层设置在第一沟槽的表面上，第一导电层嵌入第一沟槽中。 第二导电层设置在第一导电层上并与主表面上的第一导电层对准，其中第二导电层的底表面积基本上小于第二导电层的顶表面积。

公开(公告)号：US09985105B2

公开(公告)日：2018-05-29

申请号：US15199413

申请日：2016-06-30

Applicant: Nanya Technology Corp.

Inventor： Shin-Yu Nieh ,  Tieh-Chiang Wu ,  Wei-Ming Liao ,  Jei-Cheng Huang ,  Hai-Han Hung ,  Hsiu-Chun Lee

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

Abstract: The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.

公开(公告)号：US20140264640A1

公开(公告)日：2014-09-18

申请号：US13846169

申请日：2013-03-18

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shin-Yu Nieh ,  Tieh-Chiang Wu ,  Wei-Ming Liao ,  Jei-Cheng Huang ,  Hai-Han Hung ,  Hsiu-Chun Lee

IPC: H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

Abstract: The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer.

Abstract translation: 本发明提供一种半导体器件，包括：衬底; 形成在所述基板上的U形栅介质层; 以及在U形栅极电介质层的内表面上的双功函数金属栅极层，其中双功函数金属栅极层包括第一导电型金属层和第二导电型金属层。

公开(公告)号：US08698235B2

公开(公告)日：2014-04-15

申请号：US13958620

申请日：2013-08-05

Applicant: Nanya Technology Corp.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4236 ,  H01L21/28114 ,  H01L21/76224 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66553

Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.

Abstract translation: 提供狭缝凹槽通道门。 狭缝凹槽通道门包括衬底，栅介质层，第一导电层和第二导电层。 衬底具有第一沟槽。 栅介质层设置在第一沟槽的表面上，第一导电层嵌入第一沟槽中。 第二导电层设置在第一导电层上并与主表面上的第一导电层对准，其中第二导电层的底表面积基本上小于第二导电层的顶表面积。