公开(公告)号：US20250069947A1

公开(公告)日：2025-02-27

申请号：US18945868

申请日：2024-11-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHEN PAN

IPC: H01L21/768 ,  C11D3/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: The present application discloses a semiconductor device with a composite barrier structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer having a feature opening on a substrate; a composite barrier structure in the feature opening, wherein the composite barrier structure includes a barrier layer in the feature opening and an assisting blocking layer on the barrier layer; and a conductive feature on the assisting blocking layer; wherein the barrier layer includes tantalum, and the assisting blocking layer includes copper manganese alloy.

公开(公告)号：US20230307288A1

公开(公告)日：2023-09-28

申请号：US17701938

申请日：2022-03-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHEN PAN

IPC: H01L21/768 ,  H01L21/027

CPC classification number: H01L21/76807 ,  H01L21/76829 ,  H01L21/0274 ,  H01L2221/1036 ,  G03F1/38

Abstract: The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack; and forming a via in the via opening and a trench in the trench opening. The translucent layer includes a mask opening of via feature which exposes a portion of the mask substrate. A thickness of the trench region is less than a thickness of the mask region.

公开(公告)号：US20230307289A1

公开(公告)日：2023-09-28

申请号：US17701949

申请日：2022-03-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHEN PAN

IPC: H01L21/027 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/0274 ,  H01L21/76816 ,  H01L21/76829 ,  G03F1/38 ,  H01L2221/1036

Abstract: The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.

公开(公告)号：US20230307248A1

公开(公告)日：2023-09-28

申请号：US17701927

申请日：2022-03-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHEN PAN

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/31144 ,  H01L21/76816 ,  H01L21/3086 ,  H01L21/76832 ,  H01L21/0337

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes: providing a photomask comprising an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; providing a device stack comprising a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer; forming a pre-process mask layer on the device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer comprising a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature. The method also includes performing a damascene etching process to form a via opening in the first dielectric layer and a trench opening in the second dielectric layer.

公开(公告)号：US20250014910A1

公开(公告)日：2025-01-09

申请号：US18886016

申请日：2024-09-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHEN PAN

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522

Abstract: The present application discloses a method for fabricating a semiconductor device including providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening.

公开(公告)号：US20240138139A1

公开(公告)日：2024-04-25

申请号：US18223166

申请日：2023-07-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHIH-FAN KUAN ,  WEI-CHEN PAN ,  YU-TING LIN ,  HUEI-RU LIN

IPC: H10B12/00 ,  G11C5/06

CPC classification number: H10B12/00 ,  G11C5/063

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

公开(公告)号：US20240138138A1

公开(公告)日：2024-04-25

申请号：US17973202

申请日：2022-10-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHIH-FAN KUAN ,  WEI-CHEN PAN ,  YU-TING LIN ,  HUEI-RU LIN

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/108 ,  G11C5/063

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

公开(公告)号：US20250029871A1

公开(公告)日：2025-01-23

申请号：US18909160

申请日：2024-10-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHEN PAN

IPC: H01L21/768 ,  G03F1/38 ,  H01L21/027

Abstract: A method for fabricating a semiconductor device includes: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.

公开(公告)号：US20240237326A9

公开(公告)日：2024-07-11

申请号：US17973202

申请日：2022-10-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHIH-FAN KUAN ,  WEI-CHEN PAN ,  YU-TING LIN ,  HUEI-RU LIN

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/108 ,  G11C5/063

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

公开(公告)号：US20230317468A1

公开(公告)日：2023-10-05

申请号：US17709821

申请日：2022-03-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHEN PAN

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/31144 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226

Abstract: The present application provides a reworking method of a failed hard mask layer on a via opening in a dielectric layer, including removing the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; and forming a mask layer on the top hard mask layer.