公开(公告)号：US20150303936A1

公开(公告)日：2015-10-22

申请号：US14257944

申请日：2014-04-21

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Yong Rao ,  Ahsan Aziz ,  James W. McCoy

IPC: H03M1/12 ,  G06F3/0484 ,  G06F3/0481 ,  H03K19/177 ,  H03K19/173

CPC classification number: G06F3/04842 ,  G06F3/04817 ,  H03K19/1733 ,  H03K19/17748 ,  H03M1/1215

Abstract: Various embodiments of methods and associated devices for increasing throughput in a programmable hardware element using interleaved data converters are disclosed. A device comprising a programmable hardware element may be configured to comprise a plurality N of processing portions. The device may receive an input signal, and sample the signal in an interleaved fashion, on a per sample basis, at an effective rate K, to produce N parallel data streams. The N parallel data streams may be processed in parallel by the plurality N of processing portions. Outputs of the plurality N of processing portions may be combined to produce output data. The effective rate K and/or the number N of parallel data streams may be specified by user input. Alternatively, these values may be determined automatically. For example, the effective rate K may be determined automatically based on a bandwidth of the input signal.

Abstract translation: 公开了用于增加使用交错数据转换器的可编程硬件元件中的吞吐量的方法和相关装置的各种实施例。 包括可编程硬件元件的装置可以被配置为包括多个N个处理部分。 设备可以接收输入信号，并且以有效速率K以每个采样的方式以交织的方式对信号进行采样，以产生N个并行数据流。 N个并行数据流可以由多个处理部分并行处理。 可以组合多个N个处理部分的输出以产生输出数据。 并行数据流的有效速率K和/或数量N可以由用户输入来指定。 或者，可以自动确定这些值。 例如，可以基于输入信号的带宽自动确定有效速率K.

公开(公告)号：US09477386B2

公开(公告)日：2016-10-25

申请号：US14257944

申请日：2014-04-21

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Yong Rao ,  Ahsan Aziz ,  James W. McCoy

IPC: H03M1/00 ,  G06F3/0484 ,  H03K19/177 ,  H03K19/173 ,  G06F3/0481 ,  H03M1/12

CPC classification number: G06F3/04842 ,  G06F3/04817 ,  H03K19/1733 ,  H03K19/17748 ,  H03M1/1215

Abstract: Various embodiments of methods and associated devices for increasing throughput in a programmable hardware element using interleaved data converters are disclosed. A device comprising a programmable hardware element may be configured to comprise a plurality N of processing portions. The device may receive an input signal, and sample the signal in an interleaved fashion, on a per sample basis, at an effective rate K, to produce N parallel data streams. The N parallel data streams may be processed in parallel by the plurality N of processing portions. Outputs of the plurality N of processing portions may be combined to produce output data. The effective rate K and/or the number N of parallel data streams may be specified by user input. Alternatively, these values may be determined automatically. For example, the effective rate K may be determined automatically based on a bandwidth of the input signal.

Abstract translation: 公开了用于增加使用交错数据转换器的可编程硬件元件中的吞吐量的方法和相关装置的各种实施例。 包括可编程硬件元件的装置可以被配置为包括多个N个处理部分。 设备可以接收输入信号，并且以有效速率K以每个采样的方式以交织的方式对信号进行采样，以产生N个并行数据流。 N个并行数据流可以由多个处理部分并行处理。 可以组合多个N个处理部分的输出以产生输出数据。 并行数据流的有效速率K和/或数量N可以由用户输入来指定。 或者，可以自动确定这些值。 例如，可以基于输入信号的带宽自动确定有效速率K.

公开(公告)号：US20140214911A1

公开(公告)日：2014-07-31

申请号：US13941275

申请日：2013-07-12

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Yong Rao

IPC: G06F5/01

CPC classification number: G06F17/16

Abstract: System and method for developing a circuit for QR decomposition with auxiliary functionality. A first function is included in a first program. The first function is configurable to specify an auxiliary function to be performed by a modified QR decomposition circuit in addition to QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt process. A second program is automatically generated based on configuration of the QR decomposition and the first function. The second program includes program code implementing the QR decomposition and the auxiliary function for the first function in the first program. A hardware configuration program (HCP) may be automatically generated based on the first program, including the second program, where the HCP is deployable to hardware, e.g., a programmable hardware element, thereby implementing the modified QR decomposition circuit, including the QR decomposition of the matrix A and the auxiliary function.

Abstract translation: 用辅助功能开发QR分解电路的系统和方法。 第一个功能包含在第一个程序中。 第一功能是可配置的，除了使用修改的施密特过程将矩阵A QR分解为两个矩阵Q和R之外，还可以指定由修改的QR分解电路执行的辅助功能。 基于QR分解和第一功能的配置自动生成第二程序。 第二个程序包括实现QR分解的程序代码和第一个程序中的第一个功能的辅助功能。 可以基于第一程序（包括HCP可部署到硬件的第二程序，例如可编程硬件元件）自动生成硬件配置程序（HCP），从而实现修改的QR分解电路，包括QR分解 矩阵A和辅助功能。

公开(公告)号：US09201849B2

公开(公告)日：2015-12-01

申请号：US13865357

申请日：2013-04-18

Applicant: National Instruments Corporation

Inventor： Yong Rao

IPC: G06F17/10 ,  G06F17/16

CPC classification number: G06F17/16

Abstract: System and method for computing QR matrix decomposition and inverse matrix R−1. A circuit is configured to implement a QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt (MGS) process. The circuit includes a specified portion dedicated to computing matrix Q. Matrix Q is computed via the specified portion based on first inputs using the MGS process, where the first inputs include the matrix A and possibly a scaling factor σ. The identity matrix may be scaled by the scaling factor σ, thereby generating scaled identity matrix σI. Scaled matrix σR−1 (or unscaled R−1) may be computed via the specified portion based on second inputs provided to the portion using the MGS process, where the second inputs include the (possibly scaled) identity matrix. If scaled, the scaled matrix σR−1 may be unscaled, thereby computing matrix R−1. Matrix R−1 is stored and/or output.

Abstract translation: 用于计算QR矩阵分解和逆矩阵R-1的系统和方法。 电路被配置为使用修改的格拉姆施密特（MGS）过程将矩阵A的QR分解实现为两个矩阵Q和R. 电路包括专用于计算矩阵Q的指定部分。基于使用MGS处理的第一输入，经由指定部分计算矩阵Q，其中第一输入包括矩阵A和可能的缩放因子＆sgr。 单位矩阵可以通过缩放因子＆sgr来缩放，从而生成缩放的单位矩阵＆sgr; I。 可以基于提供给使用MGS处理的部分的第二输入，通过指定部分来计算缩放矩阵和Rgr（R），其中第二输入包括（可能缩放的）单位矩阵。 如果按比例缩放，则按比例缩放的矩阵和R-1可以是非缩放的，从而计算矩阵R-1。 矩阵R-1被存储和/或输出。

公开(公告)号：US20150305029A1

公开(公告)日：2015-10-22

申请号：US14691339

申请日：2015-04-20

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Yong Rao ,  Ahsan Aziz ,  Eckhard Ohlmer ,  James W. McCoy

IPC: H04W72/04 ,  H04L5/22

CPC classification number: H04L5/22 ,  H04B7/2656 ,  H04L1/00 ,  H04L5/14 ,  H04W72/1242

Abstract: A flexible real-time scheduler for a wireless communication node, enabling the node to communicate with a remote node using dynamically variable frame structure. The scheduler continuously receives map information defining the frame structure of frames in a frame sequence. Each frame includes a plurality of slots (e.g., time slots or frequency slots). The map information specifies for each slot of each frame whether the slot is to be a transmit slot or a receive slot. The scheduler drives a transmitter to transmit during the slots assigned for transmission, and drives a receiver to receive during the slots assigned for reception. (The number of slots per frame and the size of each slot are also configurable.)

Abstract translation: 用于无线通信节点的灵活的实时调度器，使节点能够使用动态可变的帧结构与远程节点进行通信。 调度器连续地接收定义帧序列中的帧的帧结构的映射信息。 每个帧包括多个时隙（例如，时隙或频率时隙）。 映射信息为每个帧的每个时隙指定时隙是发送时隙还是接收时隙。 调度器驱动发射机在分配用于传输的时隙期间进行传输，并且在分配给接收的时隙期间驱动接收机接收接收机。 （每帧的插槽数量和每个插槽的大小也可以配置。）

公开(公告)号：US09692586B2

公开(公告)日：2017-06-27

申请号：US14691339

申请日：2015-04-20

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Yong Rao ,  Ahsan Aziz ,  Eckhard Ohlmer ,  James W. McCoy

IPC: H04W72/04 ,  H04L5/22 ,  H04B7/26 ,  H04L1/00 ,  H04W72/12 ,  H04L5/14

CPC classification number: H04L5/22 ,  H04B7/2656 ,  H04L1/00 ,  H04L5/14 ,  H04W72/1242

Abstract: A flexible real-time scheduler for a wireless communication node, enabling the node to communicate with a remote node using dynamically variable frame structure. The scheduler continuously receives map information defining the frame structure of frames in a frame sequence. Each frame includes a plurality of slots (e.g., time slots or frequency slots). The map information specifies for each slot of each frame whether the slot is to be a transmit slot or a receive slot. The scheduler drives a transmitter to transmit during the slots assigned for transmission, and drives a receiver to receive during the slots assigned for reception. (The number of slots per frame and the size of each slot are also configurable.)

公开(公告)号：US09391818B1

公开(公告)日：2016-07-12

申请号：US14856736

申请日：2015-09-17

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Yong Rao

IPC: H04L7/06 ,  H04L25/03 ,  H04L25/02 ,  H04J13/00

CPC classification number: H04J13/0059 ,  H04L25/022 ,  H04L25/0226

Abstract: Techniques are disclosed relating to generating pilot sequences for channel estimation and/or equalization. In some embodiments, a generated pilot sequence has a flat frequency response, a null portion, and low autocorrelation. In some embodiments, a method for generating the pilot sequence includes: starting with a Constant Amplitude Zero Autocorrelation (CAZAC) sequence and iteratively performing, until the result has a flat magnitude: padding the sequence with zeros, determining whether a frequency transform (FT) of the zero-padded sequence has a flat magnitude, adjusting a phase of a second sequence (that has a desired frequency response) to match a phase of the FT, determining an inverse FT of the adjusted second sequence and using a result of the inverse FT as the sequence for the next iteration. The disclosed techniques may allow efficient production of pilot sequences for use in cellular networks, for example.

Abstract translation: 公开了关于生成用于信道估计和/或均衡的导频序列的技术。 在一些实施例中，所生成的导频序列具有平坦的频率响应，零部分和低自相关。 在一些实施例中，用于产生导频序列的方法包括：以恒定幅度零自相关（CAZAC）序列开始并迭代执行，直到结果具有平坦的幅度：用零填充该序列，确定频率变换（FT） 零填充序列具有平坦的幅度，调整第二序列（具有期望的频率响应）的相位以匹配FT的相位，确定经调整的第二序列的逆FT并使用逆的结果 FT作为下一次迭代的顺序。 所公开的技术可以允许例如在蜂窝网络中有效地生成用于蜂窝网络的导频序列。

公开(公告)号：US09176931B2

公开(公告)日：2015-11-03

申请号：US13941275

申请日：2013-07-12

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Yong Rao

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: System and method for developing a circuit for QR decomposition with auxiliary functionality. A first function is included in a first program. The first function is configurable to specify an auxiliary function to be performed by a modified QR decomposition circuit in addition to QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt process. A second program is automatically generated based on configuration of the QR decomposition and the first function. The second program includes program code implementing the QR decomposition and the auxiliary function for the first function in the first program. A hardware configuration program (HCP) may be automatically generated based on the first program, including the second program, where the HCP is deployable to hardware, e.g., a programmable hardware element, thereby implementing the modified QR decomposition circuit, including the QR decomposition of the matrix A and the auxiliary function.

Abstract translation: 用辅助功能开发QR分解电路的系统和方法。 第一个功能包含在第一个程序中。 第一功能是可配置的，除了使用修改的施密特过程将矩阵A QR分解为两个矩阵Q和R之外，还可以指定由修改的QR分解电路执行的辅助功能。 基于QR分解和第一功能的配置自动生成第二程序。 第二个程序包括实现QR分解的程序代码和第一个程序中的第一个功能的辅助功能。 可以基于第一程序（包括HCP可部署到硬件的第二程序，例如可编程硬件元件）自动生成硬件配置程序（HCP），从而实现修改的QR分解电路，包括QR分解 矩阵A和辅助功能。

公开(公告)号：US20140214910A1

公开(公告)日：2014-07-31

申请号：US13865357

申请日：2013-04-18

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Yong Rao

IPC: G06F5/01

CPC classification number: G06F17/16

Abstract: System and method for computing QR matrix decomposition and inverse matrix R−1. A circuit is configured to implement a QR decomposition of a matrix A into two matrices Q and R using a Modified Gram Schmidt (MGS) process. The circuit includes a specified portion dedicated to computing matrix Q. Matrix Q is computed via the specified portion based on first inputs using the MGS process, where the first inputs include the matrix A and possibly a scaling factor σ. The identity matrix may be scaled by the scaling factor σ, thereby generating scaled identity matrix σI. Scaled matrix σR−1 (or unscaled R−1) may be computed via the specified portion based on second inputs provided to the portion using the MGS process, where the second inputs include the (possibly scaled) identity matrix. If scaled, the scaled matrix σR−1 may be unscaled, thereby computing matrix R−1. Matrix R−1 is stored and/or output.

Abstract translation: 用于计算QR矩阵分解和逆矩阵R-1的系统和方法。 电路被配置为使用修改的格拉姆施密特（MGS）过程将矩阵A的QR分解实现为两个矩阵Q和R. 电路包括专用于计算矩阵Q的指定部分。基于使用MGS处理的第一输入，经由指定部分计算矩阵Q，其中第一输入包括矩阵A和可能的缩放因子＆sgr。 单位矩阵可以通过缩放因子＆sgr来缩放，从而生成缩放的单位矩阵＆sgr; I。 可以基于提供给使用MGS处理的部分的第二输入，通过指定部分来计算缩放矩阵和Rgr（R），其中第二输入包括（可能缩放的）单位矩阵。 如果按比例缩放，则按比例缩放的矩阵和R-1可以被缩放，从而计算矩阵R-1。 矩阵R-1被存储和/或输出。