公开(公告)号：US20240411977A1

公开(公告)日：2024-12-12

申请号：US18330057

申请日：2023-06-06

Applicant: NVIDIA Corp.

Inventor： Chia-Tung HO ,  Haoxing Ren

IPC: G06F30/394 ,  G06F30/392

Abstract: Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. Routing to the external net of the circuit is performed according to the graph nodes and the graph edges.

公开(公告)号：US20240411974A1

公开(公告)日：2024-12-12

申请号：US18330139

申请日：2023-06-06

Applicant: NVIDIA Corp.

Inventor： Chia-Tung HO ,  Haoxing Ren

IPC: G06F30/392 ,  G06F30/394

Abstract: Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. Routing to the external net of the circuit is performed according to the graph nodes and the graph edges.