公开(公告)号：US20230275572A1

公开(公告)日：2023-08-31

申请号：US17680763

申请日：2022-02-25

Applicant: NVIDIA Corp.

Inventor： Tezaswi Raja ,  Prashant Singh

IPC: H03K3/037 ,  H03K3/03 ,  H03K5/01

CPC classification number: H03K3/037 ,  H03K3/0315 ,  H03K5/01 ,  H03K2005/00078

Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.

公开(公告)号：US20250004522A1

公开(公告)日：2025-01-02

申请号：US18342341

申请日：2023-06-27

Applicant: NVIDIA Corp.

Inventor： Jiale Liang ,  Prashant Singh ,  Nishit Harshad Shah ,  Daniel Nguyen ,  Kaushik Krishna Raghuraman ,  Suhas Satheesh ,  Ting Lu ,  Roman Surgutchik ,  Tezaswi Raja

IPC: G06F1/28 ,  G05F1/46 ,  G06F1/24

Abstract: A circuit includes a bandgap circuit configured to generate multiple reference voltages. A first voltage glitching detection circuit utilizes a first one of the reference voltages and a first power rail to generate a first reset signal in response to a voltage glitching attack on the first power rail, and a second voltage glitching detection circuit operates independently of the reference voltages to generate a second reset signal in response to the voltage glitching attack on the first power rail.

公开(公告)号：US11923853B2

公开(公告)日：2024-03-05

申请号：US17680763

申请日：2022-02-25

Applicant: NVIDIA Corp.

Inventor： Tezaswi Raja ,  Prashant Singh

IPC: H03K3/037 ,  H03K3/03 ,  H03K5/01 ,  H03K5/00

CPC classification number: H03K3/037 ,  H03K3/0315 ,  H03K5/01 ,  H03K2005/00078

Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.