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    ON DIE CURRENT SINK CIRCUIT FOR OVERSHOOT MITIGATION
    1.
    发明公开
    ON DIE CURRENT SINK CIRCUIT FOR OVERSHOOT MITIGATION 审中-公开

    公开(公告)号：US20240322559A1

    公开(公告)日：2024-09-26

    申请号：US18186389

    申请日：2023-03-20

    Applicant: NVIDIA Corp.

    Inventor： Tezaswi Raja ,  Abhishek B Akkur ,  Jun Gu ,  Chengcheng Liu

    IPC: H02H9/04

    CPC classification number: H02H9/045

    Abstract: An integrated circuit that includes multiple power rails with dummy loads configured on at least some of the power rails. The dummy loads are activated in response to a voltage overshoot condition on regions of the power rails at which the dummy loads are located. The dummy loads may be substituted for decoupling capacitors or other active cells at particular regions of the power rails.

    CIRCUIT STRUCTURES TO MEASURE FLIP-FLOP TIMING CHARACTERISTICS
    4.
    发明公开
    CIRCUIT STRUCTURES TO MEASURE FLIP-FLOP TIMING CHARACTERISTICS 审中-公开

    公开(公告)号：US20230275572A1

    公开(公告)日：2023-08-31

    申请号：US17680763

    申请日：2022-02-25

    Applicant: NVIDIA Corp.

    Inventor： Tezaswi Raja ,  Prashant Singh

    IPC: H03K3/037 ,  H03K3/03 ,  H03K5/01

    CPC classification number: H03K3/037 ,  H03K3/0315 ,  H03K5/01 ,  H03K2005/00078

    Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.

    Detection of Electromagnetic Fault Injection Attacks on Digital Systems
    6.
    发明公开
    Detection of Electromagnetic Fault Injection Attacks on Digital Systems 审中-公开

    公开(公告)号：US20240104252A1

    公开(公告)日：2024-03-28

    申请号：US17954616

    申请日：2022-09-28

    Applicant: NVIDIA Corp.

    Inventor： Kedar Rajpathak ,  Tezaswi Raja

    IPC: G06F21/75 ,  G06F21/52

    CPC classification number: G06F21/755 ,  G06F21/52 ,  G06F2221/034

    Abstract: Techniques are described for detecting an electromagnetic (“EM”) fault injection attack directed toward circuitry in a target digital system. In various embodiments, a first node may be coupled to first driving circuitry, and a second node may be coupled to second driving circuitry. The driving circuitry is implemented in a manner such that a logic state on the second node has greater sensitivity to an EM pulse than has a logic state on the first node. Comparison circuitry may be coupled to the first and to the second nodes to assert an attack detection output responsive to sensing a logic state on the second node that is unexpected relative to a logic state on the first node.

    Circuit structures to measure flip-flop timing characteristics
    9.
    发明授权
    Circuit structures to measure flip-flop timing characteristics 有权

    公开(公告)号：US11923853B2

    公开(公告)日：2024-03-05

    申请号：US17680763

    申请日：2022-02-25

    Applicant: NVIDIA Corp.

    Inventor： Tezaswi Raja ,  Prashant Singh

    IPC: H03K3/037 ,  H03K3/03 ,  H03K5/01 ,  H03K5/00

    CPC classification number: H03K3/037 ,  H03K3/0315 ,  H03K5/01 ,  H03K2005/00078

    Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.

    Circuit Solution for Managing Power Sequencing
    10.
    发明申请
    Circuit Solution for Managing Power Sequencing 有权

    公开(公告)号：US20210294410A1

    公开(公告)日：2021-09-23

    申请号：US17331261

    申请日：2021-05-26

    Applicant: NVIDIA Corp.

    Inventor： Kedar Rajpathak ,  Tezaswi Raja

    IPC: G06F1/3296 ,  G06F1/3206

    Abstract: A circuit includes a supply power detector in a first power domain and a ratioed inverter in the first power domain or a second, different power domain. The supply power detector includes an output coupled to an input of the ratioed inverter, and an output of the ratioed inverter provides a power sequencing signal for the second power domain.

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