公开(公告)号：US12131775B2

公开(公告)日：2024-10-29

申请号：US17678799

申请日：2022-02-23

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Stefan P Sywyk ,  Andreas Jon Gotterba ,  Jesse Wang

IPC: G11C11/412

CPC classification number: G11C11/4125

Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

公开(公告)号：US11804262B2

公开(公告)日：2023-10-31

申请号：US17350973

申请日：2021-06-17

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Andreas Jon Gotterba ,  Jesse Wang ,  Stefan P Sywyk

IPC: G11C8/08 ,  G11C11/418

CPC classification number: G11C11/418

Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.