ADAPTING FORWARD ERROR CORRECTION (FEC) OR LINK PARAMETERS FOR IMPROVED POST-FEC PERFORMANCE

    公开(公告)号:US20240364451A1

    公开(公告)日:2024-10-31

    申请号:US18770877

    申请日:2024-07-12

    CPC classification number: H04L1/0045 H04L1/203

    Abstract: Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from at least the receiver circuit or the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

    EQUALIZATION ADAPTATION SCHEMES FOR HIGH-SPEED LINKS

    公开(公告)号:US20230109793A1

    公开(公告)日:2023-04-13

    申请号:US17499300

    申请日:2021-10-12

    Abstract: A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

    Adapting forward error correction (FEC) or link parameters for improved post-FEC performance

    公开(公告)号:US12267210B2

    公开(公告)日:2025-04-01

    申请号:US18112406

    申请日:2023-02-21

    Abstract: Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

    ADAPTING FORWARD ERROR CORRECTION (FEC) OR LINK PARAMETERS FOR IMPROVED POST-FEC PERFORMANCE

    公开(公告)号:US20240214134A1

    公开(公告)日:2024-06-27

    申请号:US18112406

    申请日:2023-02-21

    CPC classification number: H04L1/203 H04L1/0045 H04L1/0071

    Abstract: Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from the receiver circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

    Decision feed forward equalization for intersymbol interference cancelation

    公开(公告)号:US11611458B1

    公开(公告)日:2023-03-21

    申请号:US17392178

    申请日:2021-08-02

    Abstract: A receiver includes a decision feed forward equalization (DFFE) system coupled to a partial response (PR) system. The partial response system generates, based on a digital signal that includes pre-cursor intersymbol interference (ISI) and post-cursor ISI introduced by a communication channel, a detected signal including a set of detected symbol values. The detected signal is equalized to a partial response. The DFFE system includes a PR inverter to generate a set of estimated transmitted symbol values based on the set of detected symbol values and DFFE circuitry to cancel the pre-cursor ISI and the post-cursor ISI from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

    FEED FORWARD FILTER EQUALIZER ADAPTATION USING A CONSTRAINED FILTER TAP COEFFICIENT VALUE

    公开(公告)号:US20230006867A1

    公开(公告)日:2023-01-05

    申请号:US17365620

    申请日:2021-07-01

    Abstract: A feed forward equalizer including a first set of filter taps having a first set of filter tap coefficients to be adapted and a second set of one or more filter taps having one or more filter tap coefficients to be constrained. The feed forward equalizer includes an adaptation component to determine a set of adapted filter tap coefficient values corresponding to the first set of filter tap coefficients and a constraint function component to determine a constrained filter tap coefficient value for the second set of the one or more filter taps having the one or more filter tap coefficients to be constrained using a constraint function based on at least a portion of the set of adapted filter tap coefficient values. The feed forward equalizer generates, based at least in part on the constrained filter tap coefficient value, an equalized signal including a set of estimated symbol values.

    Equalization adaptation schemes for high-speed links

    公开(公告)号:US11646863B2

    公开(公告)日:2023-05-09

    申请号:US17499300

    申请日:2021-10-12

    Abstract: A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

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