公开(公告)号：US12267210B2

公开(公告)日：2025-04-01

申请号：US18112406

申请日：2023-02-21

Applicant: NVIDIA Corporation

Inventor： Pervez Mirza Aziz ,  Vishnu Balan ,  Rohit Rathi

IPC: H04L41/0823 ,  H03M13/35 ,  H04L1/00 ,  H04L1/20

Abstract: Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

公开(公告)号：US20240340201A1

公开(公告)日：2024-10-10

申请号：US18745229

申请日：2024-06-17

Applicant: NVIDIA Corporation

Inventor： Vishnu Balan ,  Viswanath Annampedu ,  Pervez Mirzra Aziz

IPC: H04L25/03

CPC classification number: H04L25/03057

Abstract: A receiver includes a partial response (PR) system that receives a received signal from a transmitter over a channel and equalize the received signal such that there is a controlled relationship between consecutive values of equalized received symbols and transmitted data transmitted by the transmitter. The receiver also includes a decision feed forward equalization (DFFE) system that receives partial response signals from the PR system and cancel at least one of pre-cursor intersymbol interference (ISI) or post-cursor ISI introduced by the channel.

公开(公告)号：US20240214134A1

公开(公告)日：2024-06-27

申请号：US18112406

申请日：2023-02-21

Applicant: NVIDIA Corporation

Inventor： Pervez Mirza Aziz ,  Vishnu Balan ,  Rohit Rathi

IPC: H04L1/20 ,  H04L1/00

CPC classification number: H04L1/203 ,  H04L1/0045 ,  H04L1/0071

Abstract: Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from the receiver circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

公开(公告)号：US20230239132A1

公开(公告)日：2023-07-27

申请号：US18194355

申请日：2023-03-31

Applicant: NVIDIA Corporation

Inventor： Vishnu Balan ,  Mohammad Mobin ,  Akshay Shyam Pavagada Raghavendra ,  Pervez Mirza Aziz

IPC: H04L7/00 ,  H04L25/03 ,  H04L7/06

CPC classification number: H04L7/0058 ,  H04L7/0079 ,  H04L25/03878 ,  H04L7/0091 ,  H04L25/03006 ,  H04L7/06 ,  H04L2025/03611

Abstract: An integrated circuit for a receiving link device includes a processing device to detect, using an equalizer of the receiving link device, that a receiver (RX) pre-cursor value is outside of a threshold value based on a target RX tap value. The processing device further generates, based on the detecting, a plurality of tap messages having a plurality of up or down commands to one of decrease or increase a corresponding transmitter (TX) pre-cursor value of a transmitting link device. The processing device further causes the plurality of tap messages to be provided to a local transmitter to be transmitted to the transmitting link device. The plurality of tap messages is to cause the transmitting link device to adjust the corresponding TX pre-cursor value.

公开(公告)号：US10728062B1

公开(公告)日：2020-07-28

申请号：US16287104

申请日：2019-02-27

Applicant: Nvidia Corporation

Inventor： Eric Tyson ,  Mohammad Mobin ,  Vishnu Balan ,  Hitendra Dutt

IPC: H04L25/03 ,  H04L25/02

Abstract: In a computing system, various components/devices communicate with each other. For example, a microprocessor may communicate with memory or may communicate with another microprocessor over a link. Various factors such as the frequency and transmission speed of a signal can distort what is being communicated over a link. The problem becomes more pronounced as the transmission speed increases. To address this problem, devices on both ends of a link can cooperate to equalize the link. Equalization involves configuring the transmitting device to alter the signal being transmitted so that certain distortions introduced during transmission are negated by the time the signal arrives at the receiving device. Given that each link can have slightly different characteristics, appropriate equalization parameters need to be ascertained for each link. Introduced herein are improved techniques for performing equalization that are quick yet provide equalization parameters that are stable even in a noisy high-speed link.

公开(公告)号：US20240364451A1

公开(公告)日：2024-10-31

申请号：US18770877

申请日：2024-07-12

Applicant: NVIDIA Corporation

Inventor： Pervez Mirza Aziz ,  Vishnu Balan ,  Rohit Rathi

IPC: H04L1/00 ,  H04L1/20

CPC classification number: H04L1/0045 ,  H04L1/203

Abstract: Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from at least the receiver circuit or the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

公开(公告)号：US20230208686A1

公开(公告)日：2023-06-29

申请号：US18112401

申请日：2023-02-21

Applicant: NVIDIA Corporation

Inventor： Vishnu Balan ,  Viswanath Annampedu ,  Pervez Mirzra Aziz

IPC: H04L25/03

CPC classification number: H04L25/03057

Abstract: A receiver includes a decision feed forward equalization (DFFE) system that generates, based on a digital signal that includes at least one intersymbol interference (ISI) value introduced by a communication channel, a detected signal including a set of detected symbol values. The DFFE system cancels the at least one ISI value from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

公开(公告)号：US20230109793A1

公开(公告)日：2023-04-13

申请号：US17499300

申请日：2021-10-12

Applicant: NVIDIA Corporation

Inventor： Vishnu Balan ,  Mohammad Mobin ,  Akshay Shyam Pavagada Raghavendra ,  Pervez Mirza Aziz

IPC: H04L7/00 ,  H04L7/06 ,  H04L25/03

Abstract: A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

公开(公告)号：US11018909B2

公开(公告)日：2021-05-25

申请号：US16993180

申请日：2020-08-13

Applicant: NVIDIA CORPORATION

Inventor： Vishnu Balan ,  Mohammed Mobin ,  Rohit Rathi ,  Dai Dai

IPC: H04L27/01

Abstract: A receiver receives communications over a communication channel, which may distort an incoming communication signal. In order to counter this distortion, the frequency response of the receiver is manipulated by adjusting several frequency response parameters. Each frequency response parameter controls at least a portion of the frequency response of the receiver. The optimal values for the frequency response parameters are determined by modifying an initial set of values for the frequency response parameters through one or more of stochastic hill climbing operations until a performance metric associated with the receiver reaches a local maximum. The modified values are displaced through one or more mutation operations. The stochastic hill climbing operations may subsequently be performed on the mutated values to generate the final values for the frequency response parameters.

公开(公告)号：US10749720B1

公开(公告)日：2020-08-18

申请号：US16419996

申请日：2019-05-22

Applicant: NVIDIA CORPORATION

Inventor： Vishnu Balan ,  Mohammad Mobin ,  Rohit Rathi ,  Dai Dai

IPC: H04L27/01

Abstract: A receiver receives communications over a communication channel, which may distort an incoming communication signal. In order to counter this distortion, the frequency response of the receiver is manipulated by adjusting several frequency response parameters. Each frequency response parameter controls at least a portion of the frequency response of the receiver. The optimal values for the frequency response parameters are determined by modifying an initial set of values for the frequency response parameters through one or more of stochastic hill climbing operations until a performance metric associated with the receiver reaches a local maximum. The modified values are displaced through one or more mutation operations. The stochastic hill climbing operations may subsequently be performed on the mutated values to generate the final values for the frequency response parameters.