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公开(公告)号：US20250011160A1
公开(公告)日：2025-01-09
申请号：US18897280
申请日：2024-09-26
Applicant: Northrop Grumman Systems Corporation
Inventor： Dah-Weih Duan , Elizabeth T. Kunkee , Martin E. Roden , Laura M. Woo
Abstract: A method for fabricating a micro-electronics H-frame device is provided by micro-machining a top cover usable in the device, and micro-machining a bottom cover usable in the device. The method includes fabricating together on a front of a wafer a top surface of a top substrate, the top substrate usable in the device, and a bottom surface of a bottom substrate, the bottom substrate usable in the device, wherein the top surface of the top substrate comprises top substrate top metallization, and wherein the bottom surface of the bottom substrate comprises bottom surface bottom metallization. In addition, fabricating mid-substrate metallization, bonding the top substrate to the top cover, and bonding the bottom substrate to the bottom cover are performed. The top substrate is bonded to a top surface of the mid-substrate metallization and bonding the bottom substrate to a bottom surface of the mid-substrate metallization, thereby creating a vertical electrical connection between the top substrate and the bottom substrate.
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公开(公告)号：US20230230942A1
公开(公告)日：2023-07-20
申请号：US18123467
申请日：2023-03-20
Applicant: Northrop Grumman Systems Corporation
Inventor： Dah-Weih Duan , Elizabeth T. Kunkee , Stephane Larouche
CPC classification number: H01L23/66 , H01P1/20327 , H01L2223/6627 , H01L2223/6655
Abstract: A semiconductor technology implemented high-frequency channelized filter includes a dielectric substrate with metal traces disposed on one of two major surfaces of the substrate. An input and output port disposed on the substrate and one of the metal traces carrying a high-frequency signal to be filtered between the input and output port. Other of the metal traces are connected to the one metal trace at intervals along the length of the one metal trace each providing a reactance to the high-frequency signal where the reactance varies with frequency and additional traces of the metal traces serving as a reference ground for the one metal trace and the other metal traces. A silicon enclosure mounted to the substrate with a first planar surface with cavities in the enclosure that extend through the first surface, and internal walls within the silicon enclosure defining the cavities. A layer of conductive metal covers the first planar surface, cavities and the internal walls. The silicon enclosure having substantially continuous areas of metal on the first planar surface about the periphery of the silicon enclosure that engage corresponding areas of the additional traces about the periphery of the substrate. The cavities surround the respective other metal traces with the internal cavity walls engaging the additional traces adjacent the respective other metal traces to individually surround each of the other metal traces with a conductive metal thereby providing electromagnetic field isolation between each of the other metal traces.
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公开(公告)号：US20220278059A1
公开(公告)日：2022-09-01
申请号：US17745265
申请日：2022-05-16
Applicant: Northrop Grumman Systems Corporation
Inventor： Dah-Weih Duan , Elizabeth T. Kunkee , Stephane Larouche
Abstract: A semiconductor technology implemented high-frequency channelized filter includes a dielectric substrate with metal traces disposed on one of two major surfaces of the substrate. An input and output port disposed on the substrate and one of the metal traces carrying a high-frequency signal to be filtered between the input and output port. Other of the metal traces are connected to the one metal trace at intervals along the length of the one metal trace each providing a reactance to the high-frequency signal where the reactance varies with frequency and additional traces of the metal traces serving as a reference ground for the one metal trace and the other metal traces. A silicon enclosure mounted to the substrate with a first planar surface with cavities in the enclosure that extend through the first surface, and internal walls within the silicon enclosure defining the cavities. A layer of conductive metal covers the first planar surface, cavities and the internal walls. The silicon enclosure having substantially continuous areas of metal on the first planar surface about the periphery of the silicon enclosure that engage corresponding areas of the additional traces about the periphery of the substrate. The cavities surround the respective other metal traces with the internal cavity walls engaging the additional traces adjacent the respective other metal traces to individually surround each of the other metal traces with a conductive metal thereby providing electromagnetic field isolation between each of the other metal traces.
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公开(公告)号：US20240047388A1
公开(公告)日：2024-02-08
申请号：US18382598
申请日：2023-10-23
Applicant: Northrop Grumman Systems Corporation
Inventor： Dah-Weih Duan , Elizabeth T. Kunkee , Stephane Larouche
CPC classification number: H01L23/66 , H01P1/20327 , H01L2223/6627 , H01L2223/6655
Abstract: A semiconductor technology implemented high-frequency channelized filter includes a dielectric substrate with metal traces disposed on one of two major surfaces of the substrate. An input and output port disposed on the substrate and one of the metal traces carrying a high-frequency signal to be filtered between the input and output port. Other of the metal traces are connected to the one metal trace at intervals along the length of the one metal trace each providing a reactance to the high-frequency signal where the reactance varies with frequency and additional traces of the metal traces serving as a reference ground for the one metal trace and the other metal traces. A silicon enclosure mounted to the substrate with a first planar surface with cavities in the enclosure that extend through the first surface, and internal walls within the silicon enclosure defining the cavities. A layer of conductive metal covers the first planar surface, cavities and the internal walls. The silicon enclosure having substantially continuous areas of metal on the first planar surface about the periphery of the silicon enclosure that engage corresponding areas of the additional traces about the periphery of the substrate. The cavities surround the respective other metal traces with the internal cavity walls engaging the additional traces adjacent the respective other metal traces to individually surround each of the other metal traces with a conductive metal thereby providing electromagnetic field isolation between each of the other metal traces.
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公开(公告)号：US20220289559A1
公开(公告)日：2022-09-15
申请号：US17198700
申请日：2021-03-11
Applicant: Northrop Grumman Systems Corporation
Inventor： Dah-Weih Duan , Elizabeth T. Kunkee , Martin E. Roden , Laura M. Woo
Abstract: A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.
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Patent Agency Ranking
公开(公告)号：US09865992B2
公开(公告)日：2018-01-09
申请号：US15458375
申请日：2017-03-14
Applicant: Northrop Grumman Systems Corporation
Inventor： Robert R. Rice , Elizabeth T. Kunkee
IPC: H01L21/00 , H01S5/22 , H01S5/028 , H01S5/065 , H01S5/20 , H01L21/768 , H01L21/265 , H01L45/00 , H01L51/10 , H01L21/425
CPC classification number: H01S5/22 , H01L21/265 , H01L21/425 , H01L21/76825 , H01L45/165 , H01L51/105 , H01S5/02469 , H01S5/0287 , H01S5/0425 , H01S5/0655 , H01S5/1014 , H01S5/1053 , H01S5/1064 , H01S5/2036 , H01S2301/166
Abstract: One embodiment is a wide stripe semiconductor waveguide, which is cleaved at a Talbot length thereof, the wide stripe semiconductor waveguide having facets with mirror coatings. A system provides for selective pumping the wide stripe semiconductor waveguide to create and support a Talbot mode. In embodiments according to the present method and apparatus the gain is patterned so that a single unique pattern actually has the highest gain and hence it is the distribution that oscillates.
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公开(公告)号：US20160254649A1
公开(公告)日：2016-09-01
申请号：US15151538
申请日：2016-05-11
Applicant: Northrop Grumman Systems Corporation
Inventor： Robert R. Rice , Elizabeth T. Kunkee
CPC classification number: H01S5/22 , H01L21/265 , H01L21/425 , H01L21/76825 , H01L45/165 , H01L51/105 , H01S5/02469 , H01S5/0287 , H01S5/0425 , H01S5/0655 , H01S5/1014 , H01S5/1053 , H01S5/1064 , H01S5/2036 , H01S2301/166
Abstract: One embodiment is a wide stripe semiconductor waveguide, which is cleaved at a Talbot length thereof, the wide stripe semiconductor waveguide having facets with mirror coatings. A system provides for selective pumping the wide stripe semiconductor waveguide to create and support a Talbot mode. In embodiments according to the present method and apparatus the gain is patterned so that a single unique pattern actually has the highest gain and hence it is the distribution that oscillates.
Abstract translation: 一个实施例是宽条形半导体波导，其在其Talbot长度处被切割，宽条形半导体波导具有具有镜面涂层的刻面。 系统提供选择性地泵送宽条形半导体波导以创建和支持Talbot模式。 在根据本方法和装置的实施例中，增益被图案化，使得单个唯一图案实际上具有最高增益，因此是振荡的分布。
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公开(公告)号：US12119313B2
公开(公告)日：2024-10-15
申请号：US18382598
申请日：2023-10-23
Applicant: Northrop Grumman Systems Corporation
Inventor： Dah-Weih Duan , Elizabeth T. Kunkee , Stephane Larouche
CPC classification number: H01L23/66 , H01P1/20327 , H01L2223/6627 , H01L2223/6655
Abstract: A semiconductor technology implemented high-frequency channelized filter includes a dielectric substrate with metal traces disposed on one of two major surfaces of the substrate. An input and output port disposed on the substrate and one of the metal traces carrying a high-frequency signal to be filtered between the input and output port. Other of the metal traces are connected to the one metal trace at intervals along the length of the one metal trace each providing a reactance to the high-frequency signal where the reactance varies with frequency and additional traces of the metal traces serving as a reference ground for the one metal trace and the other metal traces. A silicon enclosure mounted to the substrate with a first planar surface with cavities in the enclosure that extend through the first surface, and internal walls within the silicon enclosure defining the cavities. A layer of conductive metal covers the first planar surface, cavities and the internal walls. The silicon enclosure having substantially continuous areas of metal on the first planar surface about the periphery of the silicon enclosure that engage corresponding areas of the additional traces about the periphery of the substrate. The cavities surround the respective other metal traces with the internal cavity walls engaging the additional traces adjacent the respective other metal traces to individually surround each of the other metal traces with a conductive metal thereby providing electromagnetic field isolation between each of the other metal traces.
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公开(公告)号：US11373965B2
公开(公告)日：2022-06-28
申请号：US16916644
申请日：2020-07-17
Applicant: Northrop Grumman Systems Corporation
Inventor： Dah-Weih Duan , Elizabeth T. Kunkee , Stephane Larouche
Abstract: An exemplary semiconductor technology implemented channelized filter includes a dielectric substrate with semiconductor fabricated metal traces on one surface, and input and output ports. A signal trace connected between the input and output port carries the signal to be filtered. Filter traces connect at intervals along the length of the signal trace to provide a reactance that varies with frequency. Ground traces provide a reference ground. A silicon enclosure with semiconductor fabricated cavities has a metal layer deposited over it. The periphery of the enclosure is dimensioned to engage corresponding ground traces about the periphery of the substrate. Walls of separate cavities enclose each of the filter traces to individually surround each thereby providing electromagnetic field isolation. Metal-to-metal conductive bonds are formed between cavity walls that engage the ground traces to establish a common reference ground. The filter traces preferably meander to minimize the footprint area of the substrate.
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10.发明申请公开(公告)号：US20210337638A1
公开(公告)日：2021-10-28
申请号：US16860642
申请日：2020-04-28
Applicant: Northrop Grumman Systems Corporation
Inventor： Elizabeth T. Kunkee , Dah-Weih Duan , Dino Ferizovic , Chunbo Zhang , Greta S. Tsai , Ming-Jong Shiau , Daniel R. Scherrer , Martn E. Roden
Abstract: An exemplary semiconductor technology implemented microwave filter includes a dielectric substrate with metal traces on one surface that function as frequency selective circuits and reference ground. Other metal traces on the other surface of the substrate also provide reference ground. Bottom and top enclosures that enclose the substrate have respective interior recesses with deposited continuous metal coatings. A plurality of metal bonding bumps or bonding wall extends outwardly from the projecting walls of the bottom and top enclosures. The bonding bumps on the bottom and top enclosures engage reference ground metal traces on respective surfaces of the substrate. As a result of applied pressure, the bonding bumps and respective reference ground metal traces together with the through-substrate vias form a metal-to-metal singly-connected ground reference structure for the entire circuitry.
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