公开(公告)号：US20130308944A1

公开(公告)日：2013-11-21

申请号：US13666521

申请日：2012-11-01

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Herbert D. Schwetman, JR. ,  Michael O. McCracken ,  Pranay Koka

IPC: H04J14/00 ,  H04J14/02

CPC classification number: G02B6/12007 ,  G02B6/3544 ,  G02B6/43 ,  G02B2006/12085 ,  G02B2006/12145 ,  G02B2006/12164 ,  H04J14/0212 ,  H04Q11/0005 ,  H04Q2011/0052

Abstract: In a multi-chip module (MCM), optical waveguides in a first plane convey modulated optical signals among integrated circuits (which are sometimes referred to as ‘chips’). Moreover, an optical-butterfly switch, optically coupled to the optical waveguides, dynamically allocates communication bandwidth among the integrated circuits. This optical-butterfly switch includes optical components in the first plane and a second plane, and optical couplers that couple the modulated optical signals to and from the first plane and the second plane. In this way, the MCM communicates the modulated optical signals among the integrated circuits without optical-waveguide crossings in a given plane.

Abstract translation: 在多芯片模块（MCM）中，第一平面中的光波导在集成电路之间传送调制的光信号（有时称为“芯片”）。 此外，光耦合到光波导的光蝶形开关动态地分配集成电路之间的通信带宽。 该光蝶形开关包括第一平面中的光学部件和第二平面，以及将调制光信号耦合到第一平面和第二平面的光耦合器。 以这种方式，MCM在集成电路中通信调制的光信号，而在给定的平面内没有光波导交叉。

公开(公告)号：US09213649B2

公开(公告)日：2015-12-15

申请号：US13625502

申请日：2012-09-24

Applicant: Oracle International Corporation

Inventor： Pranay Koka ,  David A. Munday ,  Michael O. McCracken ,  Herbert D. Schwetman, Jr.

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1072 ,  G06F2212/682

Abstract: The disclosed embodiments provide a system that performs distributed page-table lookups in a shared-memory multiprocessor system with two or more nodes, where each of these nodes includes a directory controller that manages a distinct portion of the system's address space. During operation, a first node receives a request for a page-table entry that is located at a physical address that is managed by the first node. The first node accesses its directory controller to retrieve the page-table entry, and then uses the page-table entry to calculate the physical address for a subsequent page-table entry. The first node determines the home node (e.g., the managing node) for this calculated physical address, and sends a request for the subsequent page-table entry to that home node.

Abstract translation: 所公开的实施例提供了一种在具有两个或更多个节点的共享存储器多处理器系统中执行分布式页表查找的系统，其中这些节点中的每一个包括管理系统地址空间的不同部分的目录控制器。 在操作期间，第一节点接收对位于由第一节点管理的物理地址的页表条目的请求。 第一个节点访问其目录控制器以检索页表条目，然后使用页表条目计算后续页表条目的物理地址。 第一节点确定该计算出的物理地址的归属节点（例如，管理节点），并且向该家庭节点发送对后续页表条目的请求。

公开(公告)号：US20140089572A1

公开(公告)日：2014-03-27

申请号：US13625502

申请日：2012-09-24

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Pranay Koka ,  David A. Munday ,  Michael O. McCracken ,  Herbert D. Schwetman, JR.

IPC: G06F12/08

CPC classification number: G06F12/1009 ,  G06F12/1072 ,  G06F2212/682

Abstract: The disclosed embodiments provide a system that performs distributed page-table lookups in a shared-memory multiprocessor system with two or more nodes, where each of these nodes includes a directory controller that manages a distinct portion of the system's address space. During operation, a first node receives a request for a page-table entry that is located at a physical address that is managed by the first node. The first node accesses its directory controller to retrieve the page-table entry, and then uses the page-table entry to calculate the physical address for a subsequent page-table entry. The first node determines the home node (e.g., the managing node) for this calculated physical address, and sends a request for the subsequent page-table entry to that home node.

Abstract translation: 所公开的实施例提供了一种在具有两个或更多个节点的共享存储器多处理器系统中执行分布式页表查找的系统，其中这些节点中的每一个包括管理系统地址空间的不同部分的目录控制器。 在操作期间，第一节点接收对位于由第一节点管理的物理地址的页表条目的请求。 第一个节点访问其目录控制器以检索页表条目，然后使用页表条目计算后续页表条目的物理地址。 第一节点确定该计算出的物理地址的归属节点（例如，管理节点），并且向该家庭节点发送对后续页表条目的请求。

公开(公告)号：US09390016B2

公开(公告)日：2016-07-12

申请号：US13665826

申请日：2012-10-31

Applicant: Oracle International Corporation

Inventor： Pranay Koka ,  Michael O. McCracken ,  Herbert D. Schwetman, Jr. ,  Ronald Ho

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0848 ,  G06F12/0893

Abstract: The disclosed embodiments provide a system in which a processor chip accesses an off-chip cache via silicon photonic waveguides. The system includes a processor chip and a cache chip that are both coupled to a communications substrate. The cache chip comprises one or more cache banks that receive cache requests from a structure in the processor chip optically via a silicon photonic waveguide. More specifically, the silicon photonic waveguide is comprised of waveguides in the processor chip, the communications substrate, and the cache chip, and forms an optical channel that routes an optical signal directly from the structure to a cache bank in the cache chip via the communications substrate. Transmitting optical signals from the processor chip directly to cache banks on the cache chip facilitates reducing the wire latency of cache accesses and allowing each cache bank on the cache chip to be accessed with uniform latency.

Abstract translation: 所公开的实施例提供了一种系统，其中处理器芯片通过硅光子波导访问片外高速缓存。 该系统包括耦合到通信基板的处理器芯片和高速缓存芯片。 高速缓存芯片包括一个或多个高速缓存组，其经由硅光子波导光学地从处理器芯片中的结构接收高速缓存请求。 更具体地，硅光子波导由处理器芯片，通信基板和高速缓存芯片中的波导构成，并且形成光信道，其通过通信将光信号直接从结构路由到高速缓存芯片中的高速缓存组 基质。 将来自处理器芯片的光信号直接发送到高速缓存芯片上的高速缓存存储体，有助于减少高速缓存访​​问的线延迟，并允许以均匀延迟访问缓存芯片上的每个高速缓存组。

公开(公告)号：US09229163B2

公开(公告)日：2016-01-05

申请号：US13666521

申请日：2012-11-01

Applicant: Oracle International Corporation

Inventor： Herbert D. Schwetman, Jr. ,  Michael O. McCracken ,  Pranay Koka

IPC: G02B6/12 ,  G02B6/35 ,  G02B6/43 ,  H04J14/02 ,  H04Q11/00

CPC classification number: G02B6/12007 ,  G02B6/3544 ,  G02B6/43 ,  G02B2006/12085 ,  G02B2006/12145 ,  G02B2006/12164 ,  H04J14/0212 ,  H04Q11/0005 ,  H04Q2011/0052

Abstract: In a multi-chip module (MCM), optical waveguides in a first plane convey modulated optical signals among integrated circuits (which are sometimes referred to as ‘chips’). Moreover, an optical-butterfly switch, optically coupled to the optical waveguides, dynamically allocates communication bandwidth among the integrated circuits. This optical-butterfly switch includes optical components in the first plane and a second plane, and optical couplers that couple the modulated optical signals to and from the first plane and the second plane. In this way, the MCM communicates the modulated optical signals among the integrated circuits without optical-waveguide crossings in a given plane.

Abstract translation: 在多芯片模块（MCM）中，第一平面中的光波导在集成电路之间传送调制的光信号（有时称为“芯片”）。 此外，光耦合到光波导的光蝶形开关动态地分配集成电路之间的通信带宽。 该光蝶形开关包括第一平面中的光学部件和第二平面，以及将调制光信号耦合到第一平面和第二平面的光耦合器。 以这种方式，MCM在集成电路中通信调制的光信号，而在给定的平面内没有光波导交叉。

公开(公告)号：US20140122802A1

公开(公告)日：2014-05-01

申请号：US13665826

申请日：2012-10-31

Applicant: Oracle International Corporation

Inventor： Pranay Koka ,  Michael O. McCracken ,  Herbert D. Schwetman, JR. ,  Ronald Ho

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F12/0893

Abstract: The disclosed embodiments provide a system in which a processor chip accesses an off-chip cache via silicon photonic waveguides. The system includes a processor chip and a cache chip that are both coupled to a communications substrate. The cache chip comprises one or more cache banks that receive cache requests from a structure in the processor chip optically via a silicon photonic waveguide. More specifically, the silicon photonic waveguide is comprised of waveguides in the processor chip, the communications substrate, and the cache chip, and forms an optical channel that routes an optical signal directly from the structure to a cache bank in the cache chip via the communications substrate. Transmitting optical signals from the processor chip directly to cache banks on the cache chip facilitates reducing the wire latency of cache accesses and allowing each cache bank on the cache chip to be accessed with uniform latency.

Abstract translation: 所公开的实施例提供了一种系统，其中处理器芯片通过硅光子波导访问片外高速缓存。 该系统包括耦合到通信基板的处理器芯片和高速缓存芯片。 高速缓存芯片包括一个或多个高速缓存组，其经由硅光子波导光学地从处理器芯片中的结构接收高速缓存请求。 更具体地，硅光子波导由处理器芯片，通信基板和高速缓存芯片中的波导构成，并且形成光信道，其通过通信将光信号从结构直接路由到高速缓存芯片中的高速缓存组 基质。 将来自处理器芯片的光信号直接发送到高速缓存芯片上的高速缓存存储体，有助于减少高速缓存访​​问的线延迟，并允许以均匀延迟访问缓存芯片上的每个高速缓存组。