公开(公告)号：US20040164649A1

公开(公告)日：2004-08-26

申请号：US10375975

申请日：2003-02-25

Applicant: PALO ALTO RESEARCH CENTER INCORPORATED

Inventor： Baomin Xu ,  William S. Wong

IPC: H02N002/00 ,  H01L041/04 ,  H01L041/08 ,  H01L041/18

CPC classification number: B81B3/0024 ,  B81B2201/032 ,  H01L41/094 ,  H01L41/22 ,  H01L41/313 ,  H01L41/314 ,  H01L41/337 ,  Y10T29/42 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A bimorph structure is produced by depositing a first material on a first surface of a first substrate to form a first element structure. A second material is deposited onto a surface of a second substrate to form a second element structure. Electrodes are deposited on a surface of each of the first element structure and the second element structure. The first element structure is bonded to a first transfer substrate, and the second element structure is bonded to a second transfer substrate. The first substrate is removed from the first element structure, and the second substrate is removed from the second element structure. Second side electrodes are deposited on a second surface of each of the first element structures and the second element structure. The first element structure and the second element structure are directly bonded to each other. One of the first transfer substrate and the second transfer substrate is then removed, and the surface of the element structure from which one of the transfer substrates has been removed is bonded to a final target substrate. Thereafter, the other transfer substrate is removed, and electrical connections are made. In a further embodiment, a micro-electromechanical dimensioned bimorph structure includes a first element structure, and a second element structure. A bonding layer bonds the first element structure directly to the second element structure.

Abstract translation: 通过在第一基板的第一表面上沉积第一材料以形成第一元件结构来生产双压电晶片结构。 将第二材料沉积到第二基板的表面上以形成第二元件结构。 电极沉积在第一元件结构和第二元件结构中的每一个的表面上。 第一元件结构被结合到第一转移衬底，并且第二元件结构被结合到第二转移衬底。 从第一元件结构去除第一衬底，并且从第二元件结构去除第二衬底。 第二侧电极沉积在每个第一元件结构和第二元件结构的第二表面上。 第一元件结构和第二元件结构彼此直接结合。 然后去除第一转印衬底和第二转印衬底之一，并且去除了一个转印衬底的元件结构的表面被结合到最终靶衬底。 此后，移除另一转印基板，并进行电连接。 在另一实施例中，微机电尺寸的双压电晶片结构包括第一元件结构和第二元件结构。 结合层将第一元件结构直接结合到第二元件结构。

公开(公告)号：US20040164650A1

公开(公告)日：2004-08-26

申请号：US10376544

申请日：2003-02-25

Applicant: PALO ALTO RESEARCH CENTER INCORPORATED

Inventor： Baomin Xu ,  Steven A. Buhler ,  Michael C. Weisberg ,  William S. Wong ,  Scott E. Solberg ,  Karl A. Littau ,  John S. Fitch ,  Scott A. Elrod

IPC: H01L041/08

CPC classification number: B41J2/161 ,  B41J2/1623 ,  B41J2/1632 ,  B41J2/1634 ,  B41J2/1637 ,  B41J2/1646 ,  H01L41/313 ,  H01L41/314 ,  H01L41/331 ,  H01L2221/68368 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T29/4981

Abstract: A method of producing at least one piezoelectric element includes depositing a piezoelectric ceramic material onto a surface of a first substrate to form at least one piezoelectric element structure. Then an electrode is deposited on a surface of the at least one piezoelectric element structure. Next, the at least one piezoelectric element structure is bonded to a second substrate, the second substrate being conductive or having a conductive layer. The first substrate is then removed from the at least one piezoelectric element structure and a second side electrode is deposited on a second surface of the at least one piezoelectric element structure. A poling operation is performed to provide the at least one piezoelectric element structure with piezoelectric characteristics. In another embodiment, a material for a thick film element is deposited onto a surface of a first substrate to form a thick film element structure having a thickness of between greater than 10 nullm to 100 nullm. The at least one thick film element structure is bonded to a second substrate. Thereafter, the first substrate is removed from the at least one thick film element structure using a liftoff process which includes emitting, from a radiation source (such as a laser or other appropriate device), a beam through the first substrate to an attachment interface formed between the first substrate and the at least one thick film element structure at the surface of the first substrate. The first substrate is substantially transparent at the wavelength of the beam, and the beam generates sufficient energy at the interface to break the attachment.

Abstract translation: 制造至少一个压电元件的方法包括将压电陶瓷材料沉积到第一基板的表面上以形成至少一个压电元件结构。 然后在至少一个压电元件结构的表面上沉积电极。 接下来，将至少一个压电元件结构接合到第二基板，第二基板是导电的或具有导电层。 然后从至少一个压电元件结构去除第一衬底，并且第二侧电极沉积在至少一个压电元件结构的第二表面上。 执行极化操作以向至少一个压电元件结构提供压电特性。 在另一个实施例中，用于厚膜元件的材料沉积到第一基底的表面上以形成厚度大于10um至100μm的厚膜元件结构。 所述至少一个厚膜元件结构被结合到第二基板。 此后，使用包括从辐射源（例如激光或其它合适的装置）发射通过第一基板的光束到形成的附接接口的剥离过程，从至少一个厚膜元件结构中去除第一基板， 在第一基板和第一基板的表面处的至少一个厚膜元件结构之间。 第一衬底在光束的波长处基本上是透明的，并且光束在界面处产生足够的能量以破坏附件。

公开(公告)号：US20040115861A1

公开(公告)日：2004-06-17

申请号：US10320904

申请日：2002-12-16

Applicant: Palo Alto Research Center Incorporated

Inventor： William S. Wong ,  Michael L. Chabinyc ,  Steven E. Ready ,  Michael A. Kneissl ,  Mark R. Teepe

IPC: H01L021/00 ,  H01L021/06 ,  H01L021/84

CPC classification number: B81C1/00492 ,  B01L3/502707 ,  B01L2200/12 ,  B01L2300/0654 ,  B01L2300/0663 ,  B81B2201/058 ,  G01N21/01 ,  H01L2221/68363

Abstract: A method of forming an integrated microelectronic device and a micro channel is provided. The method offers an inexpensive way of integrating devices that are usually incompatible during fabrication, a microchannel and a microelectronic structure such as an electro-optic light source, a detector or a MEMs device into a single integrated structure.

Abstract translation: 提供一种形成集成的微电子器件和微通道的方法。 该方法提供了将制造期间通常不兼容的器件，微通道和诸如电光源，检测器或MEM器件的微电子结构集成到单个集成结构中的廉价方式。

公开(公告)号：US20040036731A1

公开(公告)日：2004-02-26

申请号：US10224701

申请日：2002-08-20

Applicant: Palo Alto Research Center Incorporated

Inventor： Steven E. Ready ,  William S. Wong

IPC: B41J029/393

CPC classification number: H05K3/125 ,  H01L21/288 ,  H01L21/76838 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features. By printing each design layer in a printing direction aligned with the parallel layout features, the individual print solution droplets deposited onto the substrate do not dry before adjacent droplets are deposited. Therefore, printed patterns having accurate geometries and consistent electrical properties can be printed.

Abstract translation: 公开了通过将图案布局分离成仅具有平行布局特征的离散设计层来产生均匀平滑边缘印刷图案（例如集成电路（IC）图案）的印刷系统。 通过在与平行布置特征对齐的打印方向上打印每个设计层，沉积到基板上的各个印刷液滴在相邻液滴沉积之前不会干燥。 因此，可以印刷具有精确几何形状和一致的电性能的印刷图案。

公开(公告)号：US20040196329A1

公开(公告)日：2004-10-07

申请号：US10824994

申请日：2004-04-15

Applicant: Palo Alto Research Center Incorporated

Inventor： Steven E. Ready ,  William S. Wong

IPC: B41J002/145

CPC classification number: H05K3/125 ,  H01L21/288 ,  H01L21/76838 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features. By printing each design layer in a printing direction aligned with the parallel layout features, the individual print solution droplets deposited onto the substrate do not dry before adjacent droplets are deposited. Therefore, printed patterns having accurate geometries and consistent electrical properties can be printed.

公开(公告)号：US20040163478A1

公开(公告)日：2004-08-26

申请号：US10376527

申请日：2003-02-25

Applicant: Palo Alto Research Center Incorporated

Inventor： Baomin Xu ,  Steven A. Buhler ,  William S. Wong ,  Michael C. Weisberg ,  Scott E. Solberg ,  Karl A. Littau ,  Scott A. Elrod

IPC: G01L001/00

CPC classification number: G01N29/245 ,  B06B1/0622 ,  G01L1/16 ,  G01N29/2475 ,  G01N2291/02827 ,  G01N2291/2694 ,  H01L27/20 ,  H01L41/313 ,  H01L41/314 ,  H01L41/47

Abstract: A flexible detection/test tape includes a first flexible conductive layer, and a second flexible conductive layer positioned opposite the first conductive layer. A plurality of at least one of sensors, actuators or transducers are positioned between and are bonded to the first flexible conductive layer and the second flexible conductive layer. An insulative material is inserted around the plurality of at least one of the sensors, actuators or transducers. An electrical contact network connects to the first flexible conductive layer and the second flexible conductive layer, whereby power and control signals are provided to the flexible detection/test tape. In an alternative embodiment, a method for producing a detection/test tape includes depositing a material onto a surface of at least one first substrate to form a plurality of element structures. Electrodes are deposited on a surface of each of the plurality of element structures, and the element structures are bonded to a second substrate, where the second substrate is conductive or has a conductive layer, and the second substrate is carried on a carrier plate. The at least one first substrate is removed from the element structures and second side electrodes are deposited on a second surface of each of the plurality of element structures. An insulative material is inserted around the element structures to electrically isolate the two substrates used to bond the element structures. A second side of the element structures is then bonded to another substrate, where the other substrate is conductive or has a conductive layer. Thereafter, the carrier plate carrying the second substrate is removed.

Abstract translation: 柔性检测/测试带包括第一柔性导电层和与第一导电层相对定位的第二柔性导电层。 多个传感器，致动器或换能器中的至少一个位于第一柔性导电层和第二柔性导电层之间并且被结合到第一柔性导电层和第二柔性导电层之间。 绝缘材料插入到多个传感器，致动器或换能器中的至少一个传感器周围。 电接触网络连接到第一柔性导电层和第二柔性导电层，由此向柔性检测/测试带提供电力和控制信号。 在替代实施例中，用于产生检测/测试带的方法包括将材料沉积在至少一个第一基底的表面上以形成多个元件结构。 电极沉积在多个元件结构中的每一个的表面上，并且元件结构被结合到第二衬底，其中第二衬底是导电的或具有导电层，并且第二衬底承载在载体板上。 从元件结构中去除至少一个第一衬底，并且将第二侧电极沉积在多个元件结构中的每一个的第二表面上。 绝缘材料插入在元件结构周围以电隔离用于结合元件结构的两个基板。 然后将元件结构的第二面接合到另一个衬底，其中另一个衬底是导电的或具有导电层。 此后，移除携带第二基板的承载板。