公开(公告)号：US12112808B2

公开(公告)日：2024-10-08

申请号：US18179372

申请日：2023-03-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Szu-Wei Chen ,  An-Cin Li ,  Yu-Hung Lin ,  Kai-Wei Tsou

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483

Abstract: A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.

公开(公告)号：US20250123773A1

公开(公告)日：2025-04-17

申请号：US18504107

申请日：2023-11-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jian Ping Syu ,  Wei Lin ,  Szu-Wei Chen ,  An-Cin Li

IPC: G06F3/06

Abstract: A memory operation method, a memory storage device, and a memory control circuit unit are disclosed. The memory operation includes following steps. First data is received from a host system. The first data is stored into a first physical unit which is mapped to a first logical unit. In a first operation mode, a target calculation is performed based on the first data and second data stored in a second physical unit to obtain third data, and the third data is different from the first data. The third data is stored into a third physical unit which is also mapped to the first logical unit. The third data is transmitted to the host system.

公开(公告)号：US20250060872A1

公开(公告)日：2025-02-20

申请号：US18461534

申请日：2023-09-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Jian Ping Syu ,  Szu-Wei Chen ,  An-Cin Li

IPC: G06F3/06

Abstract: A data storage method, a host system, and a data storage system are disclosed. The method includes the following. An artificial intelligence (AI) model is executed. First data to be stored to a memory storage device is obtained. In response to the first data being generated by the AI model, second data is generated according to the first data, in which the second data includes the first data, and a data amount of the second data is greater than a data amount of the first data. A first write command is sent to the memory storage device according to the second data, so as to instruct the memory storage device to store the second data.

公开(公告)号：US20240249778A1

公开(公告)日：2024-07-25

申请号：US18179372

申请日：2023-03-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Szu-Wei Chen ,  An-Cin Li ,  Yu-Hung Lin ,  Kai-Wei Tsou

IPC: G11C16/26 ,  G06F3/06 ,  G06F11/10 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483

Abstract: A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.