公开(公告)号：US20240312949A1

公开(公告)日：2024-09-19

申请号：US18306971

申请日：2023-04-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kang-Yun Yang ,  Yang-Tse Hung ,  Chao-Cheng Ku ,  Li-Yuan Lee

IPC: H01L23/00 ,  G11C5/06 ,  G11C16/14

CPC classification number: H01L24/49 ,  G11C5/06 ,  G11C16/14 ,  H01L2224/4912

Abstract: A layout structure of differential lines, a memory storage device and a memory control circuit unit are provided. The layout structure of the differential lines includes a wiring layer, a first wire and a second wire. The first wire is arranged on the wiring layer and configured to transmit a first differential signal. The second wire is arranged on the wiring layer and configured to transmit a second differential signal. A first end of the first wire and a first end of the second wire are coupled to a first electrical component. A second end of the first wire and a second end of the second wire are coupled to a second electrical component. The first end of the first wire has a first bending structure. One of the second end of the first wire and the second end of the second wire has a second bending structure.