公开(公告)号：US11238902B2

公开(公告)日：2022-02-01

申请号：US16858748

申请日：2020-04-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chien Ho Liao

IPC: G11C5/02 ,  G11C11/406 ,  G11C5/06

Abstract: A circuit layout structure and a memory storage device are disclosed. The circuit layout structure includes a plurality of first volatile memory modules, a plurality of second volatile memory modules, a first data line, a second data line, a first clock enable signal line and a second clock enable signal line. The first data line is configured to access the first volatile memory modules in parallel by a first sequential bit group. The second data line is configured to access the second volatile memory modules in parallel by a second sequential bit group. The first clock enable signal line and the second clock enable signal line are configured to control the first volatile memory modules and the second volatile memory modules to enter a self-refresh mode respectively.

公开(公告)号：US20210295877A1

公开(公告)日：2021-09-23

申请号：US16858748

申请日：2020-04-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chien Ho Liao

IPC: G11C5/02 ,  G11C5/06 ,  G11C11/406

Abstract: A circuit layout structure and a memory storage device are disclosed. The circuit layout structure includes a plurality of first volatile memory modules, a plurality of second volatile memory modules, a first data line, a second data line, a first clock enable signal line and a second clock enable signal line. The first data line is configured to access the first volatile memory modules in parallel by a first sequential bit group. The second data line is configured to access the second volatile memory modules in parallel by a second sequential bit group. The first clock enable signal line and the second clock enable signal line are configured to control the first volatile memory modules and the second volatile memory modules to enter a self-refresh mode respectively.