公开(公告)号：US11907529B2

公开(公告)日：2024-02-20

申请号：US17671597

申请日：2022-02-15

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Min Huang ,  Kuo-Hwa Ho ,  Shih-Ying Song

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: obtaining a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed; obtaining a second weight value corresponding to at least one second command being executed; and in response to a sum of the first weight value and the second weight value being greater than a base value, delaying an execution of the first command.

公开(公告)号：US12292825B2

公开(公告)日：2025-05-06

申请号：US17726474

申请日：2022-04-21

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Min Huang ,  Shih-Ying Song

IPC: G06F12/02 ,  G06F13/16

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: generating a first operation command via one of a plurality of processing circuits, wherein the first operation command instructs to access a first memory group in a plurality of memory groups; and in response to a first state information, sending a first command sequence to the first memory group according to the first operation command to instruct the first memory group to perform an access operation. The first state information reflects a first activation state of the plurality of memory groups, and the first command sequence does not include a control command sequence configured to activate the first memory group.

公开(公告)号：US20230221863A1

公开(公告)日：2023-07-13

申请号：US17671597

申请日：2022-02-15

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Min Huang ,  Kuo-Hwa Ho ,  Shih-Ying Song

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: obtaining a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed; obtaining a second weight value corresponding to at least one second command being executed; and in response to a sum of the first weight value and the second weight value being greater than a base value, delaying an execution of the first command.

公开(公告)号：US11599457B1

公开(公告)日：2023-03-07

申请号：US17583198

申请日：2022-01-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Min Huang

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/16

Abstract: A decoding circuit module, a memory control circuit unit, and a memory storage device are disclosed. The decoding circuit module is configured to decode data read from a rewritable non-volatile memory module and the decoding circuit module includes a first buffer, a second buffer, a first decoding circuit, and a second decoding circuit. The first decoding circuit is configured to decode first data read from the rewritable non-volatile memory module and stored in the first buffer. The second decoding circuit is configured to decode second data read from the rewritable non-volatile memory module and stored in the second buffer. A data decoding ability of the first decoding circuit is different from a data decoding ability of the second decoding circuit. The second data is stored in the second buffer via the first buffer and is not decoded by the first decoding circuit.

公开(公告)号：US20230281114A1

公开(公告)日：2023-09-07

申请号：US17726474

申请日：2022-04-21

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sheng-Min Huang ,  Shih-Ying Song

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0238 ,  G06F13/1668 ,  G06F2212/2022

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: generating a first operation command via one of a plurality of processing circuits, wherein the first operation command instructs to access a first memory group in a plurality of memory groups; and in response to a first state information, sending a first command sequence to the first memory group according to the first operation command to instruct the first memory group to perform an access operation. The first state information reflects a first activation state of the plurality of memory groups, and the first command sequence does not include a control command sequence configured to activate the first memory group.