公开(公告)号：US20190214367A1

公开(公告)日：2019-07-11

申请号：US15867613

申请日：2018-01-10

Applicant: Powertech Technology Inc.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu ,  Li-Chih Fang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/28 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/28 ,  H01L23/5384 ,  H01L23/552 ,  H01L25/50

Abstract: A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

公开(公告)号：US20170358557A1

公开(公告)日：2017-12-14

申请号：US15434071

申请日：2017-02-16

Applicant: Powertech Technology Inc.

Inventor： Yu-Wei Chen ,  Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/04 ,  H01L25/00

CPC classification number: H01L23/3114 ,  H01L23/04 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15331 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A POP structure includes a first package structure, an interposer, and a second package structure. The first package structure includes a first carrier, a first chip, conductive structures, and a first insulation encapsulation. The first carrier has a first surface and a second surface opposite to the first surface. The first chip and the conductive structures are disposed on the first surface of the first carrier. The first insulation encapsulation is formed on the first surface of the first carrier and encapsulates the conductive structures and the first chip. Top surfaces of the conductive structures are exposed through the first insulation encapsulation and are coplanar. The interposer is disposed on and electrically connected to the first package structure. The second package structure is disposed on and electrically connected to the interposer. A manufacturing method of a POP structure is also provided.

公开(公告)号：US10424526B2

公开(公告)日：2019-09-24

申请号：US15782857

申请日：2017-10-13

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L23/31 ,  H01L21/52 ,  H01L23/055 ,  H01L21/288 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/12 ,  H01L23/488 ,  H01L23/00 ,  H01L23/16 ,  H01L21/60

Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.

公开(公告)号：US10276553B2

公开(公告)日：2019-04-30

申请号：US15787712

申请日：2017-10-19

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L25/00 ,  H01L23/053 ,  H01L23/055 ,  H01L23/28 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L23/49 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L23/04 ,  H01L23/433

Abstract: A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

公开(公告)号：US20180114783A1

公开(公告)日：2018-04-26

申请号：US15787712

申请日：2017-10-19

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L25/10 ,  H01L23/04 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

公开(公告)号：US20180114782A1

公开(公告)日：2018-04-26

申请号：US15717953

申请日：2017-09-28

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Hsien-Wen Hsu

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/49 ,  H01L21/56 ,  H01L25/00

Abstract: A manufacturing method of a package-on package structure including at least the following steps is provided. A die is bonded on a first circuit carrier. A spacer is disposed on the die. The spacer and the first circuit carrier are connected through a plurality of conductive wires. An encapsulant is formed to encapsulate the die, the spacer and the conductive wires. A thickness of the encapsulant is reduced until at least a portion of each of the conductive wires is removed to form a first package structure. A second package structure is stacked on the first package structure. The second package structure is electrically connected to the conductive wires.

公开(公告)号：US20180114704A1

公开(公告)日：2018-04-26

申请号：US15782862

申请日：2017-10-13

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

公开(公告)号：US20190214366A1

公开(公告)日：2019-07-11

申请号：US15867577

申请日：2018-01-10

Applicant: Powertech Technology Inc.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/13026 ,  H01L2224/95001 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582

Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

公开(公告)号：US20180114781A1

公开(公告)日：2018-04-26

申请号：US15717944

申请日：2017-09-28

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/50 ,  H01L23/49 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.

公开(公告)号：US20190244934A1

公开(公告)日：2019-08-08

申请号：US16386276

申请日：2019-04-17

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/76805 ,  H01L23/3107 ,  H01L24/08 ,  H01L24/17 ,  H01L2224/02371

Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.