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公开(公告)号：US20200003802A1
公开(公告)日：2020-01-02
申请号：US16024925
申请日：2018-07-02
Applicant: Powertech Technology Inc.
Inventor： Ping-Che Lee , Ying-Tang Chao
IPC: G01R1/04
Abstract: A testing socket including a circuit board having a by-pass circuit and testing pins is provided. The circuit board includes a core dielectric layer, a power plane, and a ground plane. The core dielectric layer has a first surface and a second surface opposite to the first surface. The power plane is located on the first surface of the core dielectric layer, and the power plane is electrically connected to the by-pass circuit. The ground plane is located on the second surface of the core dielectric layer. The testing pins penetrates the circuit board, wherein two ends of each the testing pins are protruding out of the circuit board, a first group of the testing pins are electrically connected to the power plane, and a second group of the testing pins are electrically isolated from the power plane.
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公开(公告)号：US10021784B1
公开(公告)日：2018-07-10
申请号：US15846443
申请日：2017-12-19
Applicant: POWERTECH TECHNOLOGY INC.
Inventor： Ping-Che Lee , Ying-Tang Chao
CPC classification number: H05K1/112 , H05K1/09 , H05K2201/09218 , H05K2201/09227 , H05K2201/09381 , H05K2201/09409 , H05K2201/10734
Abstract: An electronic device and an electronic circuit board thereof is disclosed. In the electronic circuit board an insulation substrate is provided with conductive pads, first conductive vias, second conductive vias, third conductive vias, first conductive traces, second conductive traces, and third conductive traces. The conductive pads are arranged in two rows. Each row includes biasing pads and signal pads. The second conductive vias and the third conductive vias are respectively arranged inside and outside the first conductive vias. Each of the signal pads arranged in a row nearest the second conductive vias electrically connects with one second conductive via through a first conductive trace. Each of the signal pads arranged in a row nearest the third conductive vias electrically connects with one third conductive via through a second conductive trace. The third conductive traces embedded in the insulation substrate are extended to positions vertically under the signal pads.
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公开(公告)号：US11693043B2
公开(公告)日：2023-07-04
申请号：US17467045
申请日：2021-09-03
Applicant: Powertech Technology Inc.
Inventor： Ying-Tang Chao , Yen-Yu Chen , Shin-Kung Chen
CPC classification number: G01R31/2601 , G01R1/07314
Abstract: A test head assembly for a semiconductor device has a carrier, a pin seat and a test wire assembly. The carrier is formed in an L shape and has a lateral board, a perpendicular board and a opening formed through the perpendicular board. The pin seat is mounted in the corresponding opening. The test wire assembly has a test head, a plurality of connectors and a plurality of test wires. The test head is mounted on an outer sidewall of the lateral board and connected to the pin seat through the test wires and the connectors. Therefore, the pin seat is mounted on the perpendicular board of the L-shaped uprightly and the test head is mounted on the lateral board. The pin seat and the test head are not parallel to each other, and a lateral size of the test head assembly is reduced to increase the space usage.
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