公开(公告)号：US20200003802A1

公开(公告)日：2020-01-02

申请号：US16024925

申请日：2018-07-02

Applicant: Powertech Technology Inc.

Inventor： Ping-Che Lee ,  Ying-Tang Chao

IPC: G01R1/04

Abstract: A testing socket including a circuit board having a by-pass circuit and testing pins is provided. The circuit board includes a core dielectric layer, a power plane, and a ground plane. The core dielectric layer has a first surface and a second surface opposite to the first surface. The power plane is located on the first surface of the core dielectric layer, and the power plane is electrically connected to the by-pass circuit. The ground plane is located on the second surface of the core dielectric layer. The testing pins penetrates the circuit board, wherein two ends of each the testing pins are protruding out of the circuit board, a first group of the testing pins are electrically connected to the power plane, and a second group of the testing pins are electrically isolated from the power plane.

公开(公告)号：US10021784B1

公开(公告)日：2018-07-10

申请号：US15846443

申请日：2017-12-19

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ping-Che Lee ,  Ying-Tang Chao

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/09

CPC classification number: H05K1/112 ,  H05K1/09 ,  H05K2201/09218 ,  H05K2201/09227 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/10734

Abstract: An electronic device and an electronic circuit board thereof is disclosed. In the electronic circuit board an insulation substrate is provided with conductive pads, first conductive vias, second conductive vias, third conductive vias, first conductive traces, second conductive traces, and third conductive traces. The conductive pads are arranged in two rows. Each row includes biasing pads and signal pads. The second conductive vias and the third conductive vias are respectively arranged inside and outside the first conductive vias. Each of the signal pads arranged in a row nearest the second conductive vias electrically connects with one second conductive via through a first conductive trace. Each of the signal pads arranged in a row nearest the third conductive vias electrically connects with one third conductive via through a second conductive trace. The third conductive traces embedded in the insulation substrate are extended to positions vertically under the signal pads.

公开(公告)号：US20190052489A1

公开(公告)日：2019-02-14

申请号：US15672289

申请日：2017-08-08

Applicant: Powertech Technology Inc.

Inventor： Chih-Hui Yeh ,  Ping-Che Lee ,  Fu-Hsiang Chang

IPC: H04L25/49 ,  H04L7/00 ,  H04L7/033 ,  G08C19/28

Abstract: The communication interface including a data encoder. The data encoder receives a data package which has at least one first output signal with N bits, generates and outputs at least one transmitting signal during one period of a reference clock signal and determining a voltage level of the transmitting signal according to a logic value of the first output signal, wherein N is an integer larger than 1.