公开(公告)号：US10021784B1

公开(公告)日：2018-07-10

申请号：US15846443

申请日：2017-12-19

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ping-Che Lee ,  Ying-Tang Chao

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/09

CPC classification number: H05K1/112 ,  H05K1/09 ,  H05K2201/09218 ,  H05K2201/09227 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/10734

Abstract: An electronic device and an electronic circuit board thereof is disclosed. In the electronic circuit board an insulation substrate is provided with conductive pads, first conductive vias, second conductive vias, third conductive vias, first conductive traces, second conductive traces, and third conductive traces. The conductive pads are arranged in two rows. Each row includes biasing pads and signal pads. The second conductive vias and the third conductive vias are respectively arranged inside and outside the first conductive vias. Each of the signal pads arranged in a row nearest the second conductive vias electrically connects with one second conductive via through a first conductive trace. Each of the signal pads arranged in a row nearest the third conductive vias electrically connects with one third conductive via through a second conductive trace. The third conductive traces embedded in the insulation substrate are extended to positions vertically under the signal pads.

公开(公告)号：US20180098420A1

公开(公告)日：2018-04-05

申请号：US15549107

申请日：2015-08-20

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Kenichi KUBOYAMA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/40

CPC classification number: H05K1/0248 ,  H01L23/32 ,  H01L25/04 ,  H01L25/18 ,  H01L2224/16225 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/113 ,  H05K1/119 ,  H05K1/141 ,  H05K1/16 ,  H05K1/18 ,  H05K1/181 ,  H05K1/182 ,  H05K3/4046 ,  H05K7/02 ,  H05K2201/09218 ,  H05K2201/10378

Abstract: A semiconductor device according to an embodiment has a first semiconductor component and a second semiconductor component which are electrically connected with each other via an interposer. The interposer has a plurality of first signal wiring paths, and a plurality of second signal wiring paths each having a path distance smaller than each of the plurality of first signal wiring paths. Furthermore, the first semiconductor component includes a first electrode, a second electrode, and a third electrode arranged in order in a first direction. Furthermore, the second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode arranged in order in the first direction. Furthermore, the first electrode is connected with the fourth electrode via the first signal wiring path, the second electrode is connected with the fifth electrode via the first signal wiring path, and the third electrode is connected with the sixth electrode via the first signal wiring path.

公开(公告)号：US20180084652A1

公开(公告)日：2018-03-22

申请号：US15819289

申请日：2017-11-21

Applicant: International Business Machines Corporation

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Phillip V. Mann ,  Kevin M. O'Connell

IPC: H05K3/42 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/42 ,  H05K1/0216 ,  H05K1/11 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/09218 ,  H05K2201/09545 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a via plug with a specialized geometry and including a capillary is inserted into each via to allow electroplating on only preferred wall surfaces of the vias. Then a board plating process of the PCB manufacturing is performed.

公开(公告)号：US20180048047A1

公开(公告)日：2018-02-15

申请号：US15603582

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon Yong LEE ,  Yeon Sik YU ,  Il Kim ,  Keon Young SEO ,  Min-Goo SEO ,  Jae-Deok LIM ,  Si Ho JANG ,  Hyun-Tae JANG

IPC: H01P7/08 ,  H05K1/11 ,  H05K1/03 ,  H05K1/02

CPC classification number: H01P7/082 ,  H01P1/2005 ,  H05K1/0219 ,  H05K1/0227 ,  H05K1/0236 ,  H05K1/0353 ,  H05K1/115 ,  H05K2201/09218 ,  H05K2201/09618 ,  H05K2201/09781

Abstract: A split resonator and a printed circuit board (PCB) including the same are disclosed. The split resonator is mounted to one side of the PCB to improve the electromagnetic shielding effect, and absorbs a radiation field emitted to the outer wall of the PCB. The PCB includes: a substrate on which one or more electronic components are populated; a dielectric substrate mounted to one side of the substrate; one pair of conductors provided in the dielectric substrate, spaced apart from the substrate in a thickness direction of the substrate by a predetermined distance, and arranged to face each other; and a connection portion configured to interconnect the one pair of conductors, and arranged in parallel to the thickness direction of the substrate.

公开(公告)号：US09748625B2

公开(公告)日：2017-08-29

申请号：US15285625

申请日：2016-10-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato ,  Satoshi Ishino ,  Jun Sasaki ,  Kuniaki Yosui ,  Takahiro Baba ,  Nobuo Ikemoto

IPC: H01P3/02 ,  H01P5/00 ,  H05K1/02 ,  H05K1/14 ,  H01P3/08 ,  H05K3/36 ,  H01P5/02

CPC classification number: H01P3/02 ,  H01P3/003 ,  H01P3/026 ,  H01P3/08 ,  H01P3/082 ,  H01P3/085 ,  H01P5/00 ,  H01P5/028 ,  H05K1/0218 ,  H05K1/0221 ,  H05K1/0237 ,  H05K1/0242 ,  H05K1/025 ,  H05K1/028 ,  H05K1/0296 ,  H05K1/14 ,  H05K1/148 ,  H05K1/186 ,  H05K3/361 ,  H05K2201/0707 ,  H05K2201/09218

Abstract: A transmission line portion of a flat cable includes first regions and second regions connected alternately. In the first region, the transmission line portion is a flexible tri-plate transmission line including a dielectric element including a signal conductor, a first ground conductor including opening portions, and a second ground conductor which is a solidly filled conductor. In the second region, the transmission line portion is a hard tri-plate transmission line including a wide dielectric element including a meandering conductor, and a first ground conductor and a second ground conductor which are solidly filled conductors. A variation width of the characteristic impedance in the second region is larger than a variation width of the characteristic impedance in the first region.

公开(公告)号：US20170170799A1

公开(公告)日：2017-06-15

申请号：US14966635

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Wil Choon Song

IPC: H03H7/38 ,  H05K1/18 ,  G06F17/50 ,  H01P3/08 ,  G06F13/38 ,  H05K3/00 ,  H05K1/02

CPC classification number: H03H7/38 ,  G06F13/382 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/82 ,  H01P3/026 ,  H01P3/08 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0224 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/18 ,  H05K3/0005 ,  H05K9/0039 ,  H05K2201/09218 ,  H05K2201/0929 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09681

Abstract: Techniques for reducing multi-reflection noise via compensation structures are described herein. An example system includes a capacitive component. The example system further includes a capacitive compensation structure coupled to two ends of the capacitive component. The example system includes a partially meshed ground plane coupled to one side of a dielectric substrate. The example system also includes one or more signal conductors coupled to another side of the dielectric substrate and electrically coupled to the capacitive component. The one or more signal conductors are located parallel to a meshed length of the partially meshed ground plane.

公开(公告)号：US20160007477A1

公开(公告)日：2016-01-07

申请号：US14769574

申请日：2014-03-06

Applicant: DIS CORPORATION

Inventor： Sunao Yoshihara ,  Haruhiko Katsuta ,  Yoshinori Katayama ,  Jun Shirakami ,  Akira Murakawa ,  Wataru Fujikawa ,  Yukie Saitou

IPC: H05K3/18 ,  C25D5/02 ,  H05K3/12 ,  H05K1/09 ,  H05K1/03 ,  C25D5/56 ,  C25D7/00

CPC classification number: H05K3/188 ,  C25D5/02 ,  C25D5/56 ,  C25D7/00 ,  H05K1/0313 ,  H05K1/097 ,  H05K3/12 ,  H05K3/207 ,  H05K3/246 ,  H05K2201/0203 ,  H05K2201/0224 ,  H05K2201/0257 ,  H05K2201/09218 ,  H05K2203/0108 ,  H05K2203/097

Abstract: There is provided a method for forming an electrically conductive ultrafine pattern which has an excellent pattern cross-sectional shape is provided by a composite technique including a printing process and a plating process, and furthermore, by imparting excellent adhesion to each interface of a laminate including a plating core pattern, an electrically conductive ultrafine pattern which can be preferably used as a highly accurate electric circuit and a method for manufacturing the same are also provided. The method includes (1) a step of applying a resin composition to form a receiving layer on a substrate; (2) a step of printing an ink containing plating core particles by a reverse offset printing method to form a plating core pattern on the receiving layer; and (3) a step of depositing a metal on the plating core pattern formed in the step (2) by an electrolytic plating method.

Abstract translation: 提供了一种形成导电超细纹图案的方法，其具有优异的图案横截面形状，其通过包括印刷工艺和电镀工艺的复合技术提供，此外，通过赋予层压体的每个界面优异的粘附性，包括 还提供了电镀芯图案，可优选用作高精度电路的导电超细图案及其制造方法。 该方法包括（1）在基板上涂布树脂组合物以形成接收层的步骤; （2）通过反胶印方法印刷含有电镀芯颗粒的油墨的步骤，以在接收层上形成电镀芯图案; 和（3）通过电解电镀法在步骤（2）中形成的镀覆芯图案上沉积金属的步骤。

公开(公告)号：US09049787B2

公开(公告)日：2015-06-02

申请号：US13745352

申请日：2013-01-18

Applicant: Molex Incorporated

Inventor： Mark Alan Bugg

IPC: H05K1/09 ,  H05K1/02 ,  H01R9/03 ,  H01R13/6474

CPC classification number: H05K1/0216 ,  H01R9/032 ,  H01R12/57 ,  H01R12/62 ,  H01R12/775 ,  H01R13/6474 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/112 ,  H05K1/117 ,  H05K3/3405 ,  H05K2201/09218 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09727 ,  H05K2201/10356

Abstract: A paddle card construction disclosed for use in connecting electronic devices together. The paddle card takes the form of a circuit board that has a plurality of conductive contact pads arranged thereon in pairs. The contact pads of each pair are spaced apart from each other to provide a pair of points to which cable wire free ends may be terminated, such as by soldering. The spacing of the pads apart from each other in effect reduces to amount of capacitance in the cable wire termination area on the circuit board, thereby reducing the impedance and insertion loss in that area at high frequencies. The contact pads of each pair may be further interconnected together by a thin, conductive trace that extends lengthwise between the contact pads.

Abstract translation: 公开的用于将电子设备连接在一起的桨卡结构。 桨卡采取电路板的形式，其具有成对地布置在其上的多个导电接触垫。 每对的接触垫彼此间隔开以提供一对点，电缆线自由端可以通过焊接方式终止于该点。 彼此分开的焊盘的间隔实际上减少到电路板上的电缆线端接区域中的电容量，从而降低了在该区域的高频下的阻抗和插入损耗。 每对的接触垫可以通过在接触垫之间纵向延伸的薄导电迹线进一步互连在一起。

公开(公告)号：US20140202751A1

公开(公告)日：2014-07-24

申请号：US13745352

申请日：2013-01-18

Applicant: Molex Incorporated

Inventor： Mark Alan BUGG

IPC: H01R4/02 ,  H05K1/02

CPC classification number: H05K1/0216 ,  H01R9/032 ,  H01R12/57 ,  H01R12/62 ,  H01R12/775 ,  H01R13/6474 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/112 ,  H05K1/117 ,  H05K3/3405 ,  H05K2201/09218 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09727 ,  H05K2201/10356

Abstract: A paddle card construction disclosed for use in connecting electronic devices together. The paddle card takes the form of a circuit board that has a plurality of conductive contact pads arranged thereon in pairs. The contact pads of each pair are spaced apart from each other to provide a pair of points to which cable wire free ends may be terminated, such as by soldering. The spacing of the pads apart from each other in effect reduces to amount of capacitance in the cable wire termination area on the circuit board, thereby reducing the impedance and insertion loss in that area at high frequencies. The contact pads of each pair may be further interconnected together by a thin, conductive trace that extends lengthwise between the contact pads.

Abstract translation: 公开的用于将电子设备连接在一起的桨卡结构。 桨卡采取电路板的形式，其具有成对地布置在其上的多个导电接触垫。 每对的接触垫彼此间隔开以提供一对点，电缆线自由端可以通过焊接方式终止于该点。 彼此分开的焊盘的间隔实际上减少到电路板上的电缆线端接区域中的电容量，从而降低了在该区域的高频下的阻抗和插入损耗。 每对的接触垫可以通过在接触垫之间纵向延伸的薄导电迹线进一步互连在一起。

公开(公告)号：US20230380051A1

公开(公告)日：2023-11-23

申请号：US18246292

申请日：2021-06-29

Applicant: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.

Inventor： Liliang TIAN

IPC: H05K1/02 ,  H03B5/18

CPC classification number: H05K1/0243 ,  H03B5/18 ,  H05K1/0215 ,  H05K2201/10075 ,  H05K2201/10287 ,  H05K2201/09218

Abstract: The present disclosure discloses a crystal oscillator circuit on a PCB. The crystal oscillator circuit includes a crystal oscillator including an input end, an output end, a first grounding end and a second grounding end; a first capacitor with one end connected to the input end; and a second capacitor with one end connected to the output end, wherein the first grounding end is connected to a first grounding hole, the second grounding end is connected to a second grounding hole, the other end of the first capacitor is connected to a third grounding hole, the other end of the second capacitor is connected to a fourth grounding hole. The present disclosure further discloses the PCB and a server.